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An 8T cell is proposed to improve reliability and radiation tolerance of the static random access memory (SRAM) physical unclonable function (PUF) which is formed by adding two cascode pMOS transistors biased at the ON-state to standard 6T cell. Two custom SRAM PUFs in the same batch consisting of 6T cells and 8T cells using the 28 nm fully depleted silicon on insulator (FDSOI) process were used to evaluate the characteristics with respect to bit error rate (BER) and interchip Hamming distance (HD) with an increase in Co-60 total ionizing dose (TID), various supply voltages, ramp-up time, and temperature. According to the experimental result, the BER of the proposed SRAM PUF decreased by $2\times $ under various conditions with better radiation tolerance compared with the 6T one. Both kinds of SRAM PUF have similar interchip HD closed to 50%, but the proposed prototype has less variation, thanks to better reliability. When supply voltage, ramp-up time, and temperature conditions were set to 400 mV, 100 ms, and 25 °C, respectively, the proposed SRAM PUF can achieve the lowest BER of only 0.72%. Some design tips of reliable and rad-hard SRAM PUF are given as design guidance. [ABSTRACT FROM AUTHOR]

The dependence of temperature and back-gate bias on single-event upset (SEU) sensitivity is investigated based on a 0.2- $\mu \text{m}$ double silicon-on-insulator (DSOI) technology. At room temperature, an obvious decrease in SEU cross section with the negative back-gate bias is experimentally observed for a DSOI static random access memory (SRAM). The physical mechanism of single-event effect (SEE) is explained through technology computer-aided design (TCAD) simulations. TCAD simulations were also performed to explain the impact of back-gate bias on charge collection and full width at half maximum (FWHM) of the pulsewidth at various temperatures. Both charge collection and FWHM of the pulsewidth increase significantly with temperature rising from 240 to 400 K. It is demonstrated that the SEU threshold linear energy transfer (LET) for a DSOI 6T SRAM cell decreases with an increase in temperature. Compared with a fully depleted SOI (FDSOI) technology, the unique independent back-gate bias scheme for a DSOI SRAM cell exhibits higher tolerance to SEU. At 400 K, it is found that the SEU threshold LET (LETth) for a DSOI 6T SRAM cell increases by 12.5% with back-gate bias of nMOS reduced from 0 to −15 V. [ABSTRACT FROM AUTHOR]

Three-dimensional TCAD device simulation is carried out to study single-event effects in silicon nanowire devices. The results show that charge collection appears in silicon nanowire devices following the incidence of heavy ions, which is similar to what is observed in a traditional MOSFET. The charge collection mechanism is analyzed in detail. We find that a significant amplification bipolar effect exists in the charge collection process, enhancing the charge collection manifold. The effects of the doping type and the channel length on the charge collection are studied, and the charge collection is compared with that in bulk CMOS transistors. Furthermore, single-event responses are studied in an inverter consisting of nanowire transistors. [ABSTRACT FROM PUBLISHER]

We propose a new method to extract the gain of the parasitic bipolar transistor in ultrathin fully-depleted silicon-on-insulator MOSFETs. The method is based on the modulation of the parasitic bipolar effect by back-gate biasing. The bipolar gain can be determined for each transistor, without the need to compare the long and short devices. The proposed method is validated by experimental data and numerical simulations. [ABSTRACT FROM PUBLISHER]