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Experimental-modeling investigation of the transient thermal crosstalk between the field-effect transistors implemented on a silicon-on-insulator substrate is reported. The measurements were performed using a high-speed electrical pulse—probe sampling technique, which allowed detection of thermally modulated subthreshold currents. The technique achieved a temperature resolution of ∼50 mK, a time resolution of 5 ns, and a temperature sensitivity of ∼0.6 μA/K. The finite-element method was used to solve the heat diffusion equation and to obtain the temperature profiles for the given device structures. The combined high-resolution experimental—simulation approach allowed the study of the thermal crosstalk between two adjacent devices and probe the local temperature at different locations of the structure. The effects of the interface quality, layer thickness, material selection, and interdevice spacing on the heat diffusion and device performance were investigated in detail. [ABSTRACT FROM AUTHOR]

Various nonplanar, multigate field-effect transistors (FET) structures have been reported that offer better gate con- trol than planar MOSFETs. In the nanometer regime, however, multigate (nanowire) structures also suffer strong quantum con- finement, which causes deleterious effects such as large threshold voltage variation. In this paper, we propose a general approach to compare planar versus nonplanar FETs with the consideration of both electrostatic integrity (gate control) and quantum confinement (the so-called "EQ approach"). With this EQ approach, we show that the cylindrical wire FET and the planar double-gate MOSFET have approximately equal scaling capability for a (001)-oriented wafer, while the nonplanar wire structures are significantly better for other wafer orientations [e.g., (011)] where the effective mass in the confinement direction of the planar MOSFET is relatively small. [ABSTRACT FROM AUTHOR]