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In this article, we have comprehensively investigated the electrical properties of split-gate trench (SGT) power MOSFETs under mechanical strains. The static and dynamic electrical properties of SGT power MOSFETs under both uniaxial and biaxial strains are examined thoroughly. It is found that both uniaxial and biaxial compressive strains improve the drain current (${I}_{d}$), while uniaxial and biaxial tensile strains do the opposite. The influence of strain is correlated with drain voltage (${V}_{d}$), and biaxial strains are slightly more effective than uniaxial strains. The mechanical strains do not change the threshold voltage (${V}_{{\mathrm {th}}}$), breakdown voltage (BV), capacitances, and switching characteristics. The piezoresistance coefficients of the SGT power MOSFETs are evaluated. It is also proved that both biaxial and uniaxial compressive strains can effectively decrease the figure-of-merit (FOM) of SGT power MOSFETs. [ABSTRACT FROM AUTHOR]

In this letter, we comprehensively investigate the electrical properties of the 1200 V planner-gate 4H-SiC power metal–oxide–semiconductor field-effect transistors under the mechanical strains. Three kinds of strains, including the biaxial strain, uniaxial strain parallel to the gate channel, and uniaxial strain perpendicular to the gate channel, are applied using the wafer bending system. It is found that all kinds of compressive strains improve the drain current (Id) under the same gate voltage (Vg) and shift the threshold voltage (Vth) negatively, while the tensile strains decrease Id and shift Vth positively. The Vth shift mainly results from the strain modulated band structure in the poly-Si gate. Under the same overdrive gate voltage (Vov), biaxial strains merely change Id, while both the parallel and perpendicular uniaxial compressive strains enhance Id. The uniaxial compressive strain elevates the electron mobility in the inverted channel by repopulating more electrons into the valleys with a smaller conduction effective mass, which results in the current improvement. [ABSTRACT FROM AUTHOR]

In this brief, the contact etch stop layer (CESL) stressor is introduced to improve the performance of n-type lateral double-diffused MOSFET (nLDMOSFET) with various operating voltages. Three groups of nLDMOSFETs were studied to demonstrate the effects of the CESL stressor. The electrical properties were carefully characterized, and the tip-enhanced Raman spectroscopy measurements were carried out to examine the process-induced strain directly. It is found that nLDMOSFETs with the strained SiN CESL have larger output current, transconductance (gm), and higher breakdown voltage (BV). The strained SiN CESL introduces tensile strain in the device and results in the performance boosts, which are verified by negative Raman peak shift mappings and TCAD simulations. The strained SiN CESL could effectively decrease the specific ON-resistance (Ron) and improve the BV of the nLDMOSFET, due to the mobility enhancement. [ABSTRACT FROM AUTHOR]

In this paper, we report the experimental extraction of ballistic transport parameters of high-performance Germanium Nanowire nMOSFETs (Ge NWTs) with lengths ${L}_{\text {NW}} = {40}$ –100 nm, width ${W}_{\text {NW}} = {40}$ nm, and height ${H}_{\text {NW}} = {10}$ nm using temperature-dependent measurements. The extracted contact resistivity ($\rho {c}$) and sheet resistance (Rsh) imply that parasitic series resistance (${R}_{\text {SD}}$) of fabricated Ge NWTs is affected by $\rho _{c}$ of the metal-nGe (${3.42} \times {10}^{-{5}}\,\,\Omega \cdot \text {cm}^{{2}}$ at 292 K), which decreases with the increase in temperature. Ballistic efficiency (BE) is found to be 22%–47% at 292 K depending on the dimension of the device. It decreases with increased temperature and increases with ${L}_{\text {NW}}$ scaling down to 40 nm. The transition region with fluctuating BE is observed near ${L}_{\text {NW}} = {50}$ –60 nm, where the electron transport enters deeper into bthe allistic regime. BE is found to be sensitive to temperature and drops from 58% (170 K) to 37% (390 K) for ${L}_{\text {NW}} = {40}$ -nm Ge NWT. Therefore, in order to maintain the high ballisticity of the devices, it is important to optimize the device structure and eliminate the self-heating effect. [ABSTRACT FROM AUTHOR]

In this paper, we have comprehensively studied the performance boosts of both nLDMOS and pLDMOS under the mechanical strain. The electrical properties of LDMOS under the uniaxial tensile and compressive strains along the channel direction are examined thoroughly. We find that the uniaxial tensile strain benefits the nLDMOS, and the uniaxial compressive strain benefits the pLDMOS. Because the mechanical strain affects carriers’ transportation in bulk Si and inverted channel distinctly, the strain effects are strongly correlated with the gate voltage, drain voltage, and devices’ dimensions. It is found that the LDMOS with the longer gate length is more preferred for the strain. The piezoresistance coefficients of both nLDMOS and pLDMOS under the uniaxial strain are evaluated for the first time. It is also shown that the mechanical strain can enhance the drain current without the degradation of the breakdown voltage, which suggests a downshift of the ON-resistance versus breakdown voltage curve. [ABSTRACT FROM AUTHOR]

In this paper, we study the low-frequency noise in the Ge nanowire (NW) nMOSFETs with sub-100-nm channel length. The low-frequency noise with 1/ ${f}$ characteristics is proved to origin from the carriers’ mobility fluctuation. The dependences of low-frequency noise on NW geometry, channel length, equivalent oxide thickness (EOT), and channel doping concentration are examined by evaluating the Hooge parameters. It is shown that the low-frequency noise declines when the channel length of Ge NW nMOSFETs scales down, which is attributed to the electrons’ near ballistic transport. The electrons suffer more scatterings in the channels beneath the side walls of NWs or in the highly doped channels. The gate-oxide optimization is strongly demanded with the scaling down of EOT. Ultrascaled Ge NW nMOSFETs promise the enhancement of on-state performance and the suppression of low-frequency noise simultaneously. [ABSTRACT FROM AUTHOR]

In this letter, we comprehensively study the carriers’ mobility and the effect of back-gate bias ( V \textsf {bg} ) in Ge-on-insulator (GeOI) MOSFETs with various working modes, including accumulation mode (AM) nMOSFET, inversion mode (IM) nMOSFET, AM pMOSFET, and IM pMOSFET. The results show that the AM nMOSFETs and pMOSFETs have higher drain currents and carriers’ mobility. The electron mobility increases under positive V \textsf {bg} and decreases under negative V \textsf {bg} . While the hole mobility has the opposite V \textsf {bg} dependence. The carriers’ mobility of AM MOSFETs is proved to benefit more from V \textsf {bg} due to the increase of carriers’ densities. The peak mobility enhancements of more than 100% for holes and 35% for electrons are achieved in GeOI MOSFETs by applying V \textsf {bg} . [ABSTRACT FROM PUBLISHER]

We demonstrate an experimental study on the ballistic transport behavior of sub-100 nm GeOI n-MOSFETs, by adopting an ultrafast pulsed I–V system for measurement. High performance GeOI n-MOSFETs suffer severer self-heating effect and traps in the dc characterization process than in a “real” high-speed IC circuit. In this letter, the ballistic transport parameters for nanoscale Ge n-MOSFETs are extracted by the pulsed I–V method, and is compared with the SOI n-MOSFETs. The ballsiticity for Ge MOSFETs is higher than Si transistors at the same gate length L\text {G} . Furthermore, the scalability of the ballistic parameters for Ge n-MOSFETs is modeled and predicted for the sub-10-nm technology nodes. [ABSTRACT FROM PUBLISHER]

In this paper, Ge nanowire (NW) CMOS devices and circuits are analyzed in detail. Various experiment splits are studied, including device geometry parameters such as the channel lengths ( L\mathrm{ ch} ) from 100 to 40 nm, a NW height ( H\mathrm{ NW} ) of 10 nm, the NW widths ( W\mathrm{ NW} ) from 40 to 10 nm, and the dielectric equivalent oxide thicknesses (EOTs) of 2 and 5 nm, and four types of device operation modes of accumulation mode (AM) and inversion mode (IM) n-type MOSFETs and p-type MOSFETs. Benefited from the NW structure with scaled EOT, subthreshold swing (SS) as low as 64 mV/dec and maximum transconductance ( g\max ) as high as 1057~\mu \textS/\mu \textm are obtained on the Ge NW nMOSFETs. The NW pMOSFETs are also realized on the same common substrate. Furthermore, hybrid Ge NW CMOS with AM nMOSFET and IM pMOSFET is demonstrated for the first time on a Si substrate. The highest maximum voltage gain reaches 54 V/V in the Ge NW CMOS inverters. [ABSTRACT FROM PUBLISHER]

In this paper, we report, for the first time, that surface roughness scattering is not necessarily the dominant scattering mechanism in the high-normal-field region of Ge nMOSFETs. This statement is quite different from the well-recognized situation in Si MOSFETs. In Ge(100), phonon scattering is dominant in the high-field region. Thus, it is difficult to increase the high-normal-field mobility in Ge(100) nMOSFETs by controlling the interface roughness. In contrast, because Ge(111) and Ge(110) are free of intervalley phonon scattering, the high-field mobility in Ge(111) and Ge(110) nMOSFETs could be enhanced by the Ge interface engineering. Furthermore, different from that in Si nMOSFETs, mobility limited by surface roughness scattering in Ge nMOSFETs shows a strong temperature dependence due to the valley occupancy change of electrons. The results in this paper should facilitate efforts to increase the high-normal-field mobility in Ge nMOSFETs. [ABSTRACT FROM AUTHOR]

In this letter, we experimentally investigated the effects of four types of strains, uniaxial tensile strain, uniaxial compressive strain, biaxial tensile strain, and biaxial compressive strain, on the negative bias temperature instability (NBTI) degradation behaviors of Si pMOSFETs. The strains were applied using a wafer bending system to avoid processing effects on the NBTI characteristics as a result of strain engineering. We confirm experimentally, for the first time, that both uniaxial and biaxial compressive strains are advantageous in terms of the NBTI improvement in Si pMOSFETs. However, the NBTI reliability was degraded under both uniaxial and biaxial tensile strains. These results could not be explained by considering only the gate leakage current change due to the strain. The strain-induced modulation of the interaction between the carriers and Si-H bonds at the interface must also be considered. [ABSTRACT FROM AUTHOR]