1. The PowerPC 603 Microprocessor.
- Author
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Burgess, Brad, Ullah, Nasr, van Overen, Peter, and Ogden, Deene
- Subjects
- *
POWERPC microprocessors , *COMPUTER software , *CACHE memory , *COMPUTER storage devices - Abstract
Motorola Inc. and International Business Machines Corp. unveiled the first low-power version of the PowerPC family- the PowerPC 603 microprocessor. The 603 is the first processor in the PowerPC family to fully support the PowerPC Architecture. It incorporates five execution units: branch, integer, floating-point, load/store, and system register; and a pair of on-chip 8KB instruction and data caches. Since the 603 is a super-scalar microprocessor, it is capable of issuing and retiring as many as three instructions per clock to these execution units. The memory subsystem provides the instructions for the instruction fetcher and data for the load/store unit. Efficient access between the caches and memory systems is provided by the external bus interface. The 603 incorporates two 8KB, 2-way set associative, 32-byte per line on-chip caches, one for instructions and one for data. On a cache hit, the instructional cache can provide 2 instructions per cycle to the instruction queue, and the data-cache can provide up to a double-word of data to the load/store unit per cycle.
- Published
- 1994
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