1. 70-Gb/s amplitude-shift-keyed system with 10-GHz clock recovery circuit using duty cycle division multiplexing
- Author
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Makhfudzah Mokhtar, Raja Syamsul Azmir Raja Abdullah, Amin Malek Mohammadi, Ghafour Amouzad Mahdiraji, Mohamad Khazani Abdullah, Safuraa Mohd Basir, and Ahmad Fauzi Abas
- Subjects
Computer Networks and Communications ,business.industry ,Computer science ,Clock rate ,Electrical engineering ,Optical communication ,Multiplexing ,Atomic and Molecular Physics, and Optics ,Amplitude ,Hardware and Architecture ,Duty cycle ,Electrical and Electronic Engineering ,business ,Sensitivity (electronics) ,Software ,Clock recovery ,Communication channel - Abstract
The performance of ASK over DCDM for up to seven channels is reported. The aggregate bit rate of 70 Gb/s is achieved with only 160-GHz modulation bandwidth. The clock and data recovery are realized at 10-GHz clock rate, which is very economic and efficient. At 7 × 10 Gb/s, the worst receiver sensitivity of −10 dBm, OSNR of 41.5 dB and chromatic dispersion tolerance of ±7 ps/nm are achieved. Whereas, for the best channel, the receiver sensitivity, OSNR, and chromatic dispersion tolerance are −23.5 dBm, 29 dB, and ±36 ps/nm, respectively.
- Published
- 2009
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