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Purpose The purpose of this paper is to analyse the operation of p-type side gate junctionless silicon transistor (SGJLT) in accumulation region through experimental measurements and 3-D TCAD simulation results. The variation of electric field components, carrier’s concentration and valence band edge energy towards the accumulation region is explored with the aim of finding the origin of SGJLT performance in the accumulation operational condition.Design/methodology/approach The device is fabricated by atomic force microscopy nanolithography on silicon-on-insulator wafer. The output and transfer characteristics of the device are obtained using 3-D Technology Computer Aided Design (TCAD) Sentaurus software and compared with experimental measurement results. The advantages of AFM nanolithography in contact mode and Silicon on Insulator (SOI) technology were implemented to fabricate a simple structure which exhibits the behaviour of field effect transistors. The device has 200-nm channel length, 100-nm gate gap and 4 μm for the distance between the source and drain contacts. The characteristics of the fabricated device were measured using an Agilent HP4156C semiconductor parameter analyzer (SPA). A 3-D TCAD Sentaurus tool is used as the simulation platform. The Boltzmann statistics is adopted because of the low doping concentration of the channel. Hydrodynamic model is taken to be as the main transport model for all simulations, and the quantum mechanical effects are ignored. A doping dependent Masetti mobility model was also included as well as an electric field dependent model with Shockley–Read–Hall (SRH) carrier recombination/generation.Findings We have obtained that the device is a normally on state device mainly because of the lack of work functional difference between the gate and the channel. Analysis of electric field components’ variation, carrier’s concentration and valence band edge energy reveals that increasing the negative gate voltage drives the device into accumulation region; however, it is unable to increase the drain current significantly. The positive slope of the hole quasi-Fermi level in the accumulation region presents mechanism of carriers’ movement from source to drain. The influence of electric field because of drain and gate voltage on charge distribution explains a low increasing of the drain current when the device operates in accumulation regime.Originality/value The proposed side gate junctionless transistors simplify the fabrication process, because of the lack of gate oxide and physical junctions, and implement the atomic force microscopy nanolithography for fabrication process. The optimized structure with lower gap between gate and channel and narrower channel would present the output characteristics near the ideal transistors for next generation of scaled-down devices in both accumulation and depletion region. The presented findings are verified through experimental measurements and simulation results. [ABSTRACT FROM AUTHOR]

The fabrication of Double gate (DG) and Single gate (SG) Junctionless silicon nanowire transistor (JLSNWT) was investigated in this research. The transistors used silicon nanowire patterned on lightly doped (105 cm-3) p-type silicon-on-insulator (SOI) wafer fabricated with an atomic force microscope (AFM) nanolithography technique. The top Si layer has a thickness of 90 nm and a resistivity (p) of 13.5-22.5 Ω cm. The modified RCA method implemented for sample preparation. The local anodic oxidation (LAO) followed by two wet etching steps, KOH etching for Si removal and HF etching for oxide removal, have implemented to reach the structures. The writing speed and applied tip voltage were held in 0.6 μm/s and 8.5 volt respectively. Scan speed was held in 1.0 |im/s. The etching processes were elaborately optimized by 30% wt. KOH + 10% vol. IPA in appropriate time, temperature and humidity. The structure is a gated resistor turned off based on a pinch-off effect principle, when essential positive gate voltage is applied and made a sufficiently large barrier in the gating region. Negative gate voltage is unable to make significant effect on drain current to drive the device into accumulation mode. [ABSTRACT FROM AUTHOR]

In this paper, we have investigated the characteristics and transport features of junctionless lateral gate transistors via measurement and simulations. The transistor is fabricated using an atomic force microscopy (AFM) nanolithography technique on silicon-on-insulator (SOI) wafer. This work develops our previous examination of the device operation by using 3D numerical simulations to offer a better understanding of the origin of the transistor operation. We compare the experimental measurements and simulation results in the transfer characteristic and drain conductance. We also explore the behavior of the device in on and off states based on the variation of majority and minority carriers' density, electric-field components, and recombination/generation rate of carriers in the active region of the device. We show that the device is a normally on device that can force the current through a depleted region ( off state) and uses bulk conduction instead of surface conduction. We also found that due to the lateral gate design, low-doped channel, and lack of the gate oxide the electrostatic squeezing of the channel effectively forces the device into the off state, but the current improvement by accumulation of carriers is not significant. [ABSTRACT FROM AUTHOR]

In this letter, we investigate the fabrication of Silicon nanostructure patterned on lightly doped (1015 cm−3) p-type silicon-on-insulator by atomic force microscope nanolithography technique. The local anodic oxidation followed by two wet etching steps, potassium hydroxide etching for silicon removal and hydrofluoric etching for oxide removal, are implemented to reach the structures. The impact of contributing parameters in oxidation such as tip materials, applying voltage on the tip, relative humidity and exposure time are studied. The effect of the etchant concentration (10% to 30% wt) of potassium hydroxide and its mixture with isopropyl alcohol (10%vol. IPA ) at different temperatures on silicon surface are expressed. For different KOH concentrations, the effect of etching with the IPA admixture and the effect of the immersing time in the etching process on the structure are investigated. The etching processes are accurately optimized by 30%wt. KOH +10%vol. IPA in appropriate time, temperature, and humidity. [ABSTRACT FROM AUTHOR]