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Nanostructures have attracted a great deal of attention because of their potential usefulness for high density applications. More importantly, they offer excellent avenues for improved scaling beyond conventional approaches. Less attention has been paid to their intrinsic potential for distinct circuit applications. Here we discuss how a combination of 1-D transport, operation in the quantum capacitance limit, and ballistic transport can be utilized for certain RF applications. In particular this work explores how the above transport properties can provide a high degree of transconductance linearity at the device level. The article also discusses how device characteristics can be interpreted and analyzed in terms of device linearity if the above conditions are not ideally fulfilled. Using aggressively scaled silicon nanowire field-effect transistors as an example device in this work provides new insights toward the proper choice of channel material to improve linearity through the above-mentioned transport conditions. According to this study, a high degree of linearity occurs feasible while operating at low supply voltages making low-dimensional systems, and here in particular nanowires, an interesting candidate for portable RF applications.

This article provides experimental evidence of one-dimensional behavior of silicon (Si) nanowires (NWs) at low-temperature through both transfer (I(d)-V(G)) and capacitance-voltage characteristics. For the first time, operation of Si NWs in the quantum capacitance limit (QCL) is experimentally demonstrated and quantitatively analyzed. This is of relevance since working in the QCL may allow, e.g., tunneling field-effect transistors (TFETs) to achieve higher on-state currents (I(on)) and larger on-/off-state current ratios (I(on)/I(off)), thus addressing one of the most severe limitations of TFETs. Comparison of the experimental data with simulations finds excellent agreement using a simple capacitor model.

The hole surface roughness and phonon limited mobility in the silicon <100>, <110>, and <111> square nanowires under the technologically important conditions of applied gate bias and stress are studied with the self-consistent Poisson-sp3d5s*-SO tight-binding bandstructure method. Under an applied gate field, the hole carriers in a wire undergo a volume to surface inversion transition diminishing the positive effects of the high <110> and <111> valence band nonparabolicities, which are known to lead to the large gains of the phonon limited mobility at a zero field in narrow wires. Nonetheless, the hole mobility in the unstressed wires down to the 5 nm size remains competitive or shows an enhancement at high gate field over the large wire limit. Down to the studied 3 nm sizes, the hole mobility is degraded by strong surface roughness scattering in <100> and <110> wires. The <111> channels are shown to experience less surface scattering degradation. The physics of the surface roughness scattering dependence on wafer and channel orientations in a wire is discussed. The calculated uniaxial compressive channel stress gains of the hole mobility are found to reduce in the narrow wires and at the high field. This exacerbates the stressed mobility degradation with size. Nonetheless, stress gains of a factor of 2 are obtained for <110> wires down to 3 nm size at a 5×1012 cm-2 hole inversion density per gate area. [ABSTRACT FROM AUTHOR]

The effect of geometrical confinement, atomic position, and orientation of silicon nanowires (SiNWs) on their thermal properties are investigated using the phonon dispersion obtained using a Modified Valence Force Field (MVFF) model. The specific heat (Cν) and the ballistic thermal conductance (κlbal) shows anisotropic variation with changing cross-section shape and size of the SiNWs. The Cν increases with decreasing cross-section size for all the wires. The triangular wires show the largest Cν due to their highest surface-to-volume ratio. The square wires with [110] orientation show the maximum κlbal because they have the highest number of conducting phonon modes. At the nano-scale a universal scaling law for both Cν and κlbal are obtained with respect to the number of atoms in the unit cell. This scaling is independent of the shape, size, and orientation of the SiNWs, revealing a direct correlation of the lattice thermal properties to the atomistic properties of the nanowires. Thus, engineering the SiNW cross-section shape, size, and orientation open up new ways of tuning the thermal properties in the nanometer regime. [ABSTRACT FROM AUTHOR]

Engineering of the cross-section shape and size of ultra-scaled Si nanowires (SiNWs) provides an attractive way for tuning their structural properties. The acoustic and optical phonon shifts of the free-standing circular, hexagonal, square, and triangular SiNWs are calculated using a modified valence force field (MVFF) model. The acoustic phonon blue shift (acoustic hardening) and the optical phonon red shift (optical softening) show a strong dependence on the cross-section shape and size of the SiNWs. The triangular SiNWs have the least structural symmetry as revealed by the splitting of the degenerate flexural phonon modes and these show the minimum acoustic hardening and the maximum optical hardening. The acoustic hardening, in all SiNWs, is attributed to the decreasing difference in the vibrational energy distribution between the inner and the surface atoms with decreasing cross-section size. The optical softening is attributed to the reduced phonon group velocity and the localization of the vibrational energy density on the inner atoms. While the acoustic phonon shift shows a strong wire orientation dependence, the optical phonon softening is independent of wire orientation. [ABSTRACT FROM AUTHOR]

A 20 band sp3d5s* spin-orbit-coupled, semiempirical, atomistic tight-binding model is used with a semiclassical, ballistic field-effect-transistor model, to theoretically examine the bandstructure carrier velocity and ballistic current in silicon nanowire (NW) transistors. Infinitely long, uniform, cylindrical, and rectangular NWs, of cross sectional diameters/sides ranging from 3–12 nm are considered. For a comprehensive analysis, n-type and p-type metal-oxide semiconductor (NMOS and PMOS) NWs in [100], [110], and [111] transport orientations are examined. In general, physical cross section reduction increases velocities, either by lifting the heavy mass valleys or significantly changing the curvature of the bands. The carrier velocities of PMOS [110] and [111] NWs are a strong function of diameter, with the narrower D=3 nm wires having twice the velocities of the D=12 nm NWs. The velocity in the rest of the NW categories shows only minor diameter dependence. This behavior is explained through features in the electronic structure of the silicon host material. The ballistic current, on the other hand, shows the least sensitivity with cross section in the cases where the velocity has large variations. Since the carrier velocity is a measure of the effective mass and reflects on the channel mobility, these results can provide insight into the design of NW devices with enhanced performance and performance tolerant to structure geometry variations. In the case of ballistic transport in high performance devices, the [110] NWs are the ones with both high NMOS and PMOS performance as well as low on-current variations with cross section geometry variations. [ABSTRACT FROM AUTHOR]

Nanowire band-to-band tunneling field-effect transistors (TFETs) are simulated using the Wentzel–Kramers–Brillouin (WKB) approximation and an atomistic, full-band quantum transport solver including direct and phonon-assisted tunneling (PAT). It is found that the WKB approximation properly works if one single imaginary path connecting the valence band (VB) and the conduction band (CB) dominates the tunneling process as in direct band gap semiconductors. However, PAT is essential in Si and Ge nanowire TFETs where multiple, tightly-coupled, imaginary paths exist between the VB and the CB. [ABSTRACT FROM AUTHOR]

The bandstructures of [110] and [001] Bi2Te3 nanowires are solved with the atomistic 20 band tight binding functionality of NEMO5. The theoretical results reveal: The popular assumption that all topological insulator (TI) wire surfaces are equivalent is inappropriate. The Fermi velocity of chemically distinct wire surfaces differs significantly which creates an effective in-surface confinement potential. As a result, topological insulator surface states prefer specific surfaces. Therefore, experiments have to be designed carefully not to probe surfaces unfavorable to the surface states (low density of states) and thereby be insensitive to the TI-effects. [ABSTRACT FROM AUTHOR]

Traditional thinking assumes that a light effective mass ($m^*$ ), high mobility material will result in better transistor characteristics. However, sub-12-nm metal-oxide-semiconductor field effect transistors (MOSFETs) with light $m^*$ may underperform compared to standard Si, as a result of source to drain (S/D) tunneling. An optimum heavier mass can decrease tunneling leakage current, and at the same time, improve gate to channel capacitance because of an increased quantum capacitance ($C_q$ ). A single band effective mass model has been used to provide the performance trends independent of material, orientation and strain. This paper provides guidelines for achieving optimum $m^*$ for sub-12-nm nanowire down to channel length of 3 nm. Optimum $m^*$ are found to range between 0.2–1.0 $m_0$ and more interestingly, these masses can be engineered within Si for both p-type and n-type MOSFETs. $m^*$ is no longer a material constant, but a geometry and strain dependent property of the channel material. [ABSTRACT FROM PUBLISHER]

The role of alloy and phonon scattering is theoretically explored in 5 nm diameter SiGe nanowires at room temperature. Low‐field mobility calculations are performed by utilizing sp3d5ds*‐spin–orbit‐coupled tight binding model for electronic structure and Boltzmann transport formalism. Three different transport orientations 〈100〉, 〈110〉 and 〈111〉 are considered. Alloy scattering is found to play an important role in these Si1–xGex nanowires, leading to a characteristic ‘U’ shaped mobility curve as a function of alloy composition. It is concluded that to extract any advantage of higher Ge hole mobility by alloying, Ge% > 70% is needed. Furthermore, the 〈111〉 channel orientation exhibits the highest hole mobility while 〈100〉 has the lowest hole mobility for any given alloy composition. (© 2013 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim) Part of Focus Issue on “Semiconductor Nanowires” (Eds.: Chennupati Jagadish, Lutz Geelhaar, Silvija Gradecak) SiGe is an important material for high mobility p‐type transistors. In this Letter, the role of alloy and phonon scattering on the total hole mobility in SiGe nanowires is studied. At low carrier density, alloy scattering is still found to be relevant leading to an ‘U’ shaped mobility curve as a function of Ge concentration. [ABSTRACT FROM AUTHOR]

As metal-oxide-semiconductor field-effect transistors (MOSFETs) channel lengths (Lg) are scaled to lengths shorter than Lg<8~nm source-drain tunneling starts to become a major performance limiting factor. In this scenario, a heavier transport mass can be used to limit source-drain (S-D) tunneling. Taking InAs and Si as examples, it is shown that different heavier transport masses can be engineered using strain and crystal-orientation engineering. Full-band extended device atomistic quantum transport simulations are performed for nanowire MOSFETs at Lg<8~nm in both ballistic and incoherent scattering regimes. In conclusion, a heavier transport mass can indeed be advantageous in improving ON-state currents in ultrascaled nanowire MOSFETs. [ABSTRACT FROM AUTHOR]

When the physical gate length is reduced to 5 nm, direct channel tunneling dominates the leakage current for both field-effect transistors (FETs) and tunnel FETs. Therefore, a survey of materials in a nanowire geometry is performed to determine their ability to suppress the direct tunnel current through a 5 nm barrier. The materials investigated are InAs, InSb, InP, GaAs, GaN, Si, Ge, and carbon nanotubes. The tunneling effective mass gives the best indication of the relative size of the tunnel currents when comparing two different materials of any type. The indirect-gap materials, Si and Ge, give the largest tunneling masses in the conduction band, and they give the smallest conduction band tunnel currents within the range of diameters considered. Si gives the lowest overall tunnel current for both the conduction and valence bands, and therefore, it is the optimum choice for suppressing tunnel current at the 5 nm scale. A semianalytic approach to calculating tunnel current is demonstrated, which requires considerably less computation than a full-band numerical calculation. [ABSTRACT FROM AUTHOR]

The influence of interface roughness scattering (IRS) on the performances of silicon nanowire (NW) field-effect transistors is numerically investigated using a full 3-D quantum transport simulator based on an atomistic \sp^3\d^5\s^\ast tight-binding model. An interface between silicon and silicon dioxide layers is generated in a real-space atomistic representation using an experimentally derived autocovariance function. An oxide layer is modeled in a virtual crystal approximation using fictitious \SiO2 atoms. \langle \110\rangle-oriented NWs with different diameters and randomly generated surface configurations are studied. An experimentally observed on-current and threshold voltage are quantitatively captured by the simulation model. The mobility reduction due to IRS is studied through a qualitative comparison of the simulation results with the experimental data. [ABSTRACT FROM PUBLISHER]

Full-quantum device simulations on p-type Si nanowire field-effect transistors based on the k \cdot p method, using the k \cdot p parameters tuned against the sp^3s^\ast tight-binding method, are carried out. Full transport calculations from both methods agree reasonably well, and the spin-orbit coupling effect is found to be negligible in the final current–voltage characteristics. Use of the highly efficient simulator based on the \3 \times \3\ k \cdot p Hamiltonian is therefore justified, and simulations of nanowire devices with cross sections from \3 \times \3\ \nm^2 up to \10 \times \10\ \nm^2 are performed. The subthreshold characteristics, threshold voltages, and on-state currents for the three respective transport directions of the [100], [110], and [111] directions are examined. The device characteristics for the [110] and [111] directions are quite similar in every respect, and the [100] direction has the advantage with regard to the subthreshold behavior when the channel length is aggressively scaled down. The on-current magnitudes for the three respective orientations do not differ much, although the on-current in the [100] direction is a little smaller, compared with that in the other two directions when the channel width becomes smaller. An uncoupled mode space approach has been used to determine the contributions from individual heavy and light hole subbands, enabling an insightful analysis of the device characteristics. [ABSTRACT FROM PUBLISHER]

One-dimensional (1D) and two-dimensional (2D) metal-oxide-semiconductor field-effect transistors are compared using an approach based on the top-of-the-barrier ballistic transport model. The results for model devices show that 1D and 2D transistors behave quite similarly if the electrostatics is assumed to be perfect. Distinctive features of 1D transport are difficult to observe at room temperature. The effects of band structure on I-V and C-V characteristics of Si and InAs nanowire transistors are also examined using the sp3d5s* tight-binding model. It is found that band structure effects in 1D transistors are most distinctively reflected in the drain current versus gate bias or transconductance versus gate bias for low drain bias at low temperatures. Some effects may also be observed in nanowire C-V characteristics. [ABSTRACT FROM AUTHOR]

Bandstructure effects in the electronic transport of strongly quantized silicon nanowire field-effect-transistors (FET) in various transport orientations are examined. A 10-band sp3d5s* semiempirical atomistic tight-binding model coupled to a self-consistent Poisson solver is used for the dispersion calculation. A semi-classical, ballistic FET model is used to evaluate the current-voltage characteristics. It is found that the total gate capacitance is degraded from the oxide capacitance value by 30% for wires in all the considered transport orientations ([100], [110], [111]). Different wire directions primarily influence the carrier velocities, which mainly determine the relative performance differences, while the total charge difference is weakly affected. The velocities depend on the effective mass and degeneracy of the dispersions. The [110] and secondly the [100] oriented 3 mn thick nanowires examined, indicate the best ON-current performance compared to [111] wires. The dispersion features are strong functions of quantization. Effects such as valley splitting can lift the degeneracies particularly for wires with cross section sides below 3 nm. The effective masses also change significantly with quantization, and change differently for different transport orientations. For the cases of [100] and [111] wires the masses increase with quantization, however, in the [110] case, the mass decreases. The mass variations can be explained from the non-parabolicities and anisotropies that reside in the first Brillouin zone of silicon. [ABSTRACT FROM AUTHOR]

In Part I, the development and deployment of a general nanoelectronic modeling tool (NEMO 3-D) has been discussed. Based on the atomistic valence-force field and the sp³d5s* nearest neighbor tight-binding models, NEMO 3-D enables the computation of strain and electronic structure in nanostructures consisting of more than 64 and 52 million atoms, corresponding to volumes of (110 nm)³ and (101 nm)³, respectively. In this part, successful applications of NEMO 3-D are demonstrated in the atomistic calculation of single-particle electronic states of the following realistically sized nanostructures: 1) self-assembled quantum dots (QDs) including long-range strain and piezoelectricity; 2) stacked quantum dot system as used in quantum cascade lasers; 3) SiGe quantum wells (QWs) for quantum computation; and 4) SiGe nanowires. These examples demonstrate the broad NEMO 3-D capabilities and indicate the necessity of multimillion atomistic electronic structure modeling. [ABSTRACT FROM AUTHOR]

This paper examines the validity of the widely used parabolic effective-mass approximation for computing the current-voltage (I-V) characteristics of silicon nanowire transistors (SNWTs). The energy dispersion relations for unrelaxed Si nanowires are first computed by using an sp³d5S* tight-binding (TB) model. A seminumerical ballistic field-effect transistor model is then adopted to evaluate the I-V characteristics of the (n-type) SNWTs based on both a TB dispersion relation and parabolic energy bands. In comparison with the TB approach, the parabolic effective-mass model with bulk effective-masses significantly overestimates SNWT threshold voltages when the wire width is <3 nm, and ON-currents when the wire width is <5 nm. By introducing two analytical equations with two tuning parameters, however, the effective-mass approximation can well reproduce the TB I-V results even at a ∼1.36-nm wire width. [ABSTRACT FROM AUTHOR]

The electronic structure and transmission coefficients of Si nanowires are calculated in a sp³ d&sup5; s* model. The effect of wire thickness on the bandgap, conduction valley splitting, hole band splitting, effective masses, and transmission is demonstrated. Results from the sp³d&sup5;s* model are compared to those from a single-band effective mass model to assess the validity of the single- band effective mass model in narrow Si nanowires. The one-dimensional Brillouin zone of a Si nanowire is direct gap. The conduction band minimum can split into a quartet of energies although often two of the energies are degenerate. Conduction band valley splitting reduces the averaged mobility mass along the axis of the wire, but quantum confinement increases the transverse mass of the conduction band edge. Quantum confinement results in a large increase in the hole masses of the two highest valence bands. A single-band model performs reasonably well at calculating the effective band edges for wires as small as 1.54-nm square. A wire- substrate interface can be viewed as a heterojunction with band offsets resulting in reflection in the transmission. [ABSTRACT FROM AUTHOR]

We report design of double-gate metal–oxide–semiconductor field-effect-transistors having InGaAs/InAlAs superlattices between the N+ source and a planar InGaAs channel. As with nanowire superlattice transistors, the 2-D superlattice bandgap reduces injection into the channel of electrons having energy above the source Fermi energy. Simulated ballistic transport characteristics of FETs using a three-well superlattice show 29–37.5-mV/decade minimum subthreshold swing and 390-A/m ON-current given 0.1-A/m OFF-current and a 0.2 V power supply. [ABSTRACT FROM AUTHOR]

The effects of an atomistic interface roughness in n-type silicon nanowire transistors (SiNWT) on the radio frequency performance are analyzed. Interface roughness scattering (IRS) is statistically investigated through a three dimensional full-band quantum transport simulation based on the sp3d5s* tight-binding model. As the diameter of the SiNWT is scaled down below 3 nm, IRS causes a significant reduction of the cut-off frequency. The fluctuations of the conduction band edge due to the rough surface lead to a reflection of electrons through mode-mismatch. This effect reduces the velocity of electrons and hence the transconductance considerably causing a cut-off frequency reduction. [ABSTRACT FROM AUTHOR]

The impact of uniaxial and hydrostatic stress on the ballistic thermal conductance (κl) and the specific heat (Cν) of [100] and [110] Si nanowires are explored using a Modified Valence Force Field phonon model. An anisotropic behavior of κl and isotropic nature of Cν under strain are predicted for the two wire orientations. Compressive (tensile) strain decreases (increases) Cν. The Cv trend with strain is controlled by the high energy phonon sub-bands. Dominant contribution of the low/mid (low/high) energy bands in [100] ([110]) wire and their variation under strain governs the behavior of κl. [ABSTRACT FROM AUTHOR]

Lead Selenide (PbSe) is an attractive 'IV-VI' semiconductor material to design optical sensors, lasers, and thermoelectric devices. Improved fabrication of PbSe nanowires (NWs) enables the utilization of low dimensional quantum effects. The effect of cross-section size (W) and channel orientation on the band structure of PbSe NWs is studied using an 18 band sp3d5 tight-binding theory. The band gap increases almost with the inverse of the W for all the orientations indicating weak symmetry dependence. [111] and [110] NWs show higher ballistic conductance for the conduction and valence band compared to [100] NWs due to the significant splitting of the projected L-valleys in [100] NWs. [ABSTRACT FROM AUTHOR]

Porous nanowires (NWs) with tunable thermal conductance are examined as a candidate for thermoelectric devices with high efficiency. Thermal conductance (σl) of porous NWs is calculated using the phonon dispersion obtained from a modified valence force field model. Porosity in the NWs break the crystal symmetry leading to the reduction in ballistic σl. [100] Si and Ge NWs show similar percentage reductions in σl for the same amount of porosity. The model predicts an anisotropic reduction in σl in SiNWs, with [111] showing the maximum reduction followed by [100] and [110] for a similar hole radius. The reduction in σl is attributed to phonon localization and anisotropic mode reduction. [ABSTRACT FROM AUTHOR]

The performances of ultrascaled SiGe nanowire field-effect transistors (NWFETs) are investigated using an atomistic tight-binding model and a virtual crystal approximation to describe the Si and Ge atoms. It is first demonstrated that the band edges and the effective masses of both relaxed and strained SiGe bulk are accurately reproduced by our model. The band structure model is then coupled to a top-of-the-barrier quantum transport approach to simulate the output characteristics of ultrascaled n/p SiGe NWFETs and explore their viability for future high-performance CMOS applications. We predict a considerable improvement of SiGe nFETs and pFETs over their Si counterparts for SiGe/Si core/shell structures. [ABSTRACT FROM AUTHOR]

The experimental characterization of gate capacitance in nanoscale devices is challenging. We report an application of the charge-based capacitance measurement (CBCM) technique to measure the gate capacitance of a single-channel nanowire transistor. The measurement results are validated by 3-D electrostatic computations for parasitic estimation and 2-D self-consistent sp³s*d5 tight-binding computations for intrinsic gate capacitance calculations. The device simulation domains were constructed based on SEM and TEM images of the experimental device. The carefully designed CBCM technique thus emerges as a useful technique for measuring the capacitance and characterizing the transport in nanoscale devices. [ABSTRACT FROM AUTHOR]

In this letter, we explore the band structure effects on the performance of ballistic silicon nanowire transistors (SNWTs). The energy dispersion relations for silicon nanowires are evaluated with an sp3d5s* tight binding model. Based on the calculated dispersion relations, the ballistic currents for both n-type and p-type SNWTs are evaluated by using a seminumerical ballistic model. For large diameter nanowires, we find that the ballistic p-SNWT delivers half the ON-current of a ballistic n-SNWT. For small diameters, however, the ON-current of the p-type SNWT approaches that of its n-type counterpart. Finally, the carrier injection velocity for SNWTs is compared with those for planar metal-oxide-semiconductor field-effect transistors, clearly demonstrating the impact of quantum confinement on the performance limits of SNWTs. [ABSTRACT FROM AUTHOR]

Abstract: The simulation of realistically sized devices under the Non-Equilibrium Greens Function (NEGF) formalism typically requires prohibitive amounts of memory and computation time. In order to meet the rising computational challenges associated with quantum-scale device simulation we offer a 2-D domain decomposition technique. This technique is applicable to a large class of atomistic and spatial simulation problems. Considering a decomposition along both the cross section and length of the device, the framework presented in this work ensures efficient distribution of both memory and computation based upon the underlying device structure. As an illustration we stably generate the density of states and transmission, under the NEGF formalism, for the atomistic-based simulation of square 5nm cross section silicon nanowires consisting of over one million atomic orbitals. [Copyright &y& Elsevier]