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Defect in manufacturing of integrated circuits is almost inevitable, and fast scaling in technology has caused the components of a Network-on-Chip (NoC) to be more susceptible to faults. Therefore, it is crucial to sustain chip production yield and reliable operation in the presence of defects. A fault-tolerant application-specific NoC should be able to detect a fault and recover the system to correctly operate the mapped application. In this paper, a fault-tolerant NoC architecture designed in VHDL and synthesized using Xilinx ISE is presented which not only is able to recover from single permanent router failure, but also improves the average response time of the system in the different traffic loads. As hardware overhead is a major issue while considering fault tolerance, a new component, called Link Interface (LI) is also developed to reduce cost overhead. The Video Object Plan Decoder (VOPD) core graph is used as a real application in this study. [ABSTRACT FROM AUTHOR]

Mapping algorithm, which is an important phase of an NoC design tries to map most frequent and most critical communications in such a way that minimize the physical distance between the source and destination nodes. The objective of this paper is to achieve an application-specific NoC design that minimizes the communication cost and improves the fault tolerant properties. First, a heuristic mapping algorithm that produces a set of different mappings in a reasonable time is presented. Although this mapping does not explore the design space thoroughly, it considers a part of design space, which in general minimizes the communication costs of solutions while yielding optimum communication costs in some cases. Comparison of the communication cost results makes it obvious that final solutions found by our proposed approach outperform the results of other methods, which proposed in literature. Then, the used routing algorithm and the concept, vulnerability index, which is considered as a criterion for estimating the fault-tolerance of mapped application, are presented in details. Lower communication cost leads to an NoC with better metrics such as energy consumption and latency; and reducing the vulnerability index optimizes fault tolerant properties of NoC. In order to yield a mapping which considers trade-offs between these two parameters, a linear function is defined and introduced. It is also observed that more flexibility to prioritize solutions within the design space is possible by adjusting a set of if-then rules in fuzzy logic. [ABSTRACT FROM AUTHOR]