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A low-power and low noise-figure (NF) 3.1–23.7-GHz CMOS variable-gain amplifier (VGA) is presented. The VGA composes of a complimentary common-source (CCS) first stage, followed by a common-source (CS) second stage. Low power and NF and wideband $S_{11}$ and $S_{21}$ are achieved due to the current-reused CCS input stage with multiple inductive impedance matching and gain compensation. A large gain tuning range (with low NF) is achieved due to the concurrent gate–voltage tuning (or current steering) of the first and the second stages. The VGA consumes 5.85 mW (at $V_{\mathrm {ctrl}}$ of 1 V) and achieves excellent 3-dB bandwidth ($f_{3\,\mathrm {dB}}$) of 20.6 GHz (3.1–23.7 GHz), maximum $S_{21}$ of 11.9 dB, minimum NF (NFmin) of 2.53 dB, average NF (NFavg) of 3.97 dB, small group delay (GD) variation of ±16.5 ps, and input third-order intercept point (IIP3) of −6.5 dBm. Moreover, the VGA achieves a decent gain tuning range of 23.4 dB (−5.4 to 18 dB) for $V_{\mathrm {ctrl}}$ of 0.6–1.6 V. The chip area is 0.364 mm2. [ABSTRACT FROM AUTHOR]

We demonstrate a low-power $(P_{D})$ , low-noise, and high-gain 22.7–29.7-GHz variable-gain amplifier (VGA) in 90-nm CMOS for 28-GHz 5G systems. Low $P_{D}$ and wide gain tuning range are achieved due to the use of the self-body-to-drain bias through body-floating resistance and the current-reused topology with auxiliary current steering. Input noise matching and body-floating techniques are used for noise figure (NF) enhancement. VGA consumes 7.4 mW and achieves $S_{21}$ tuning range of 23.7 dB (19.2 to −4.5 dB) at 26 GHz. At $V_{\mathrm {ctrl}}$ of 0 V (i.e., maximum gain), VGA attains $S_{21}$ of 16.2–19.2 dB for 22.7–29.7 GHz [i.e., 3-dB bandwidth ($f_{3\,\mathrm {dB}}$) equal to 7 GHz], minimum noise figure (NF $_{\mathrm {min}}$) of 2.39 dB at 26.5 GHz, average NF (NF $_{\mathrm {avg}}$) of 2.76 dB for 22.5–29.5 GHz, small group delay (GD) variation of ± 14.7 ps for 18–30 GHz (i.e., decent phase linearity), and input third-order intercept point (IIP3) of −12.7 dBm at 28 GHz. The chip area is 0.383 mm2. [ABSTRACT FROM AUTHOR]

We demonstrate a low-power ($P_{D}$) and high-gain 21–29-GHz low-noise amplifier (LNA) in 90-nm CMOS for 28-GHz 5G systems. Current-reused architecture is adopted for low $P_{D}$. Gain-boosting and body-floating techniques are used for gain and NF enhancement. The LNA consumes 13.7 mW and achieves prominent $S_{21}$ of 21.6 dB, 3-dB bandwidth of 8.1 GHz (21.2–29.3 GHz), minimum noise figure (NF $_{\mathrm {min}}$) of 2.74 dB, average NF (NF $_{\mathrm {ave}}$) of 2.99 dB for 21–29 GHz, and figure of merit (FOM) of 61.7 GHz. Moreover, the LNA achieves input third-order intercept point (IIP3) of −9 dBm at 28 GHz. The chip size is only 0.348 mm2. To the authors’ knowledge, the NF and FOM performance are one of the best results ever reported for millimeter-wave CMOS LNAs with bandwidth greater than 7 GHz and $P_{D}$ lower than 15 mW. [ABSTRACT FROM AUTHOR]

A low-power, high-gain (HG), and low-noise (LN) CMOS distributed amplifier (DA) using cascaded gain cell, formed by an inductively parallel-peaking cascode-stage with a low-Q RLC load and an inductively series-peaking common-source stage, is proposed. Flat and high S21 and flat and low noise figure (NF) are achieved simultaneously by adopting a slightly under-damped Q factor for the second-order transconductance frequency response. A single-stage and a two-stage DA for ultra-wideband (UWB) systems are demonstrated. In the LN mode, the two-stage DA consumes 22 mW and achieves flat and high S21 of 14.07 \pm 1.69 dB with an average NF of only 2.8 dB over the 3–10-GHz band of interest, one of the best reported NF performances for a CMOS UWB DA or LN amplifier in the literature. In addition, in the low-gain mode, the two-stage DA consumes 6.86 mW and achieves S21 of 11.03 \pm 0.98 dB and an average NF of 4.25 dB. In the HG mode, the two-stage DA consumes 37.8 mW and achieves S21 of 20.47 \pm 0.72 dB and an average NF of 3.3 dB. The analytical, simulated, and measured results are mutually consistent. [ABSTRACT FROM AUTHOR]

We demonstrate a 1.2–8.6 GHz two-stage distributed amplifier (DA) with cascade gain cell, which constitutes two enhanced CMOS inverters, using standard 0.18 \mum CMOS technology. Multiple noise suppression techniques, including three noise-suppression/gain-peaking inductors and an RL terminal network, were used to achieve flat and low noise figure (NF) and flat and high power gain (\vertS21\vert) at the same time. At low-gain (LG) mode, the DA achieved \vertS21\vert of 11.41 \pm 1.39 dB and an average NF of 3.74 dB for frequencies 1.2 \sim 8.6 GHz with a power dissipation (PDC) of 9.85 mW. At high-gain (HG) mode, the DA consumed 46.85 mW and achieved flat and high \vertS21\vert of 17.1 \pm 1.5 dB with an average NF of 3.52 dB for frequencies 1.5 \sim 8.2 GHz. [ABSTRACT FROM PUBLISHER]