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Processing-in-memory (PIM) architecture has been proposed to accelerate state-of-the-art neuro-inspired algorithms, such as deep neural networks. In this article, we present PIMulator-NN, an event-driven, cross-level simulation framework for PIM-based neural network accelerators. By employing an event-driven simulation mechanism, PIMulator-NN is able to model architecture details and capture design details of the architecture. Moreover, we integrate the main-stream circuit-level simulation framework with PIMulator-NN to accurately simulate the area, latency, and energy consumption of analog computation units. To demonstrate the usage of PIMulator-NN, we implement several PIM designs with PIMulator-NN and perform detailed simulation. The simulation results show that memory access and interconnects make considerable impacts on system-level performance and energy. Note that such results are hard to be captured by conventional performance model-based estimations. We found some anti common-sense results while modeling the architecture details with PIMulator-NN. With several architecture templates, PIMulator-NN provides the users with a platform to build up their PIM architecture quickly. PIMulator-NN is able to capture the impacts of different design choices (e.g., dataflow, interconnect, data parallelism, etc.), and this could enable users to explore their design space efficiently. [ABSTRACT FROM AUTHOR]

In a digital–analog mixed neuromorphic system, various complex peripheral circuits may offset the integration and energy efficiency advantages of the dense crossbar. To simplify the peripheral circuits, a self-activation neural network (SANN) is proposed based on a passive crossbar array formed by the rectified memristive (ReMem) cell. The ReMem cell is a dual-mode resistive switching device with a VO2/TaOx bilayer structure. It shows a hybrid switching behavior including volatile threshold switching and multilevel nonvolatile resistive switching. This unique feature enables not only simultaneously self-selection and distributed activation, but also weight storage. The concept of SANN is theoretically examined, and a neural network is constructed and trained with SANN based on the proposed devices to perform recognition on handwritten digits in the MNIST database. Compared with neuromorphic computing systems using the CMOS-based activation module and additional selective element, the results show comparable recognition accuracy with reduced circuitry complexity. The proposed SANN can be a promising alternative to realize neural network computing systems with simplified peripheral circuits. [ABSTRACT FROM AUTHOR]

In this letter, we experimentally demonstrated a novel resistive device with a hybrid switching mode that can be alternated between volatile threshold switching and non-volatile resistive switching. The device consists of dual-functional layers VO2 /HfO2 sandwiched by symmetrical TiN electrodes. A >20 unified ratio for selectivity and memory window is obtained. Owing to the stable resistive behavior of HfO2 and insulator-metal transition of VO2, the device shows excellent uniform switching parameters in both switching modes with a high on-state current density (1E4 A/cm2) and fast switching/recovery speed (< 30 ns). This self-selective resistive memory is of great potential in the high-density crossbar array, particularly for the future 3D-Vertical resistive random access memory (RRAM) integration. [ABSTRACT FROM AUTHOR]

Crossbar array architecture is usually used for the high-density integration of the RRAM device. However, the large sneak current in the passive crossbar array limits the increase in the integration density. In this brief, the bipolar \TiN/TaOx/\Pt RRAM device is proposed as the dynamic selector for the unipolar \Pt/TaOx/\Pt RRAM device to suppress the sneak current in the crossbar array. The testing results show that the bipolar RRAM can act as a good selector, and the sneak current is reduced by about two orders estimated by the 1/2 Vread voltage scheme. With the suppressed sneak current, the maximum size of the crossbar array with the bipolar RRAM selector can be increased to more than 1 Mb according to the simulation results, indicating that the bipolar RRAM selector has great potential for the high-density memory applications. [ABSTRACT FROM AUTHOR]