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Artificial intelligence has been demonstrated for numerous applications including image recognition and processing, internet-of-things (IoT), and speech recognition. Recent neural network (NN) architectures escalating to perform these functionalities require deep-learning and deep NN (DNN) implementation. However, the present algorithm and circuit of DNN suffer from area and energy-efficiency. The usage of an energy-efficient and cost-effective binary NN (BNN) can mitigate the performance bottleneck. The basic component of BNN (the XNOR and accumulate module) is capable of replacing the conventional multiply-and-accumulate (MAC) operation. Among various emerging nonvolatile memories (NVMs), spintronics-based devices are attracting attention for the implementation of the aforementioned architectures. Multilevel voltage-controlled spin-orbit torque -based magnetic memory (MV-SOTM) spin device as synapse and voltage-controlled SOTM (V-SOTM) device as spin-neuron are capable of producing an all-spin NN. This article presents advanced XNOR operation using a computing-in-memory (CiM) mechanism wherein both V-SOTM and MV-SOTM (using series and parallel configuration) based synapses are compared. The MV-SOTM design dissipates 35.51% lesser energy as compared to the 1-bit V-SOTM. Further, the 8-bit synaptic crossbar array is implemented using both the devices with two output spin-neurons. These series and parallel MV-SOTM-based synaptic arrays consume 42.22% and 45.12% lesser power, respectively, as compared to 1-bit V-SOTM based synaptic array. Furthermore, the all-spin BNN design demonstrates a handwritten digit recognition application. [ABSTRACT FROM AUTHOR]

Spintronics, being a burgeoning area of research, aims to incorporate magnetic tunnel junction (MTJ), as a basic storage building block, to various electronic applications. In continuation of many device structure using MTJ such as spin-transfer torque (STT)-MTJ, spin Hall effect (SHE)-MTJ, spin–orbit torque (SOT)-MTJ, domain wall-based MTJ, and complementary polarizer MTJ, this paper presents a differential spin Hall effect (DSHE). The working and operational analysis of the DSHE-based memory element is presented. It provides 50% improved write energy and more than 1.5 times faster read as compared to a single-ended SHE-MTJ. The device structure is well suited for various differential circuit applications, for example, nonvolatile static random access memory (NVSRAM), nonvolatile flip flop (NVFF), magnetic full adder, and nonvolatile differential sense latch, with a fast and energy-efficient operation. In addition, DSHE-MTJ application for NVSRAM (named as DSNVM) is proposed. Performance of DSNVM is compared with the STT+SHE-based NVSRAM (named as SHENVM). DSNVM shows improved performance in terms of area overhead, restoration delay, and energy. DSNVM provides 40% faster restoration and 16.7% lesser energy as compared to SHENVM. Furthermore, a computational investigation for cell stability is depicted using butterfly curve and N-curve methods. Usually, write noise margins deteriorate in NVSRAMs due to the constituent NV cell. However, read as well as write noise margin is improved in DSNVM. [ABSTRACT FROM AUTHOR]