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Infrared focal plane arrays (IRFPA) based on HgCdTe semiconductor alloys have been shown to be ideal for tactical and strategic applications. High density (>1 M pixel), high operability HgCdTe detectors on large area, low-cost composite substrates, such as CdTe-buffered Si or GaAs, are envisioned for next-generation IRFPAs. Thermal expansion mismatch is among various material parameters that govern the structural properties of the final detector layer. It has previously been shown that thermal expansion mismatch plays the dominant role in the residual stress characteristics of these heteroepitaxial structures (Jacobs et al. in J Electron Mater 37:1480, 2008). The wafer curvature (bowing) resulting from residual stress, is a likely source of problems that may occur during subsequent processing. This includes cracking of the film and substrate during post-growth annealing processes or even certain characterization techniques. In this work, we examine dynamic curvature and stress during molecular beam epitaxy (MBE), of CdTe on Si and GaAs substrates. The effect of temperature changes on wafer curvature throughout the growth sequence is documented using a multi-beam optical sensor developed by K-Space Associates. This monitoring technique makes possible the study of growth sequences which employ annealing schemes and/or interlayers to influence the final residual stress state of the heteroepitaxial structures.

Minimization of operating bias and generation–recombination dark current in long wavelength infrared (LWIR) strained layer superlattice (SLS) detectors, consisting of a lightly doped p-type absorber layer and a wide band gap hole barrier, are investigated with respect to the band alignment between the wide band gap barrier and absorber layers. Dark current vs. bias, photoresponse, quantum efficiency, lifetime, and modeling are used to correlate device performance with the wide gap barrier composition. Decreases in dark current density and operating bias were observed as the conduction band of the wide gap barrier was lowered with respect to the absorber layer. The device achieved 95% of its maximum quantum efficiency at 0 V bias, and 100% by 0.05 V. This study demonstrates key device design parameters responsible for optimal performance of heterojunction based SLS LWIR detectors.

Design parameters for the heterojunction-based strained layer superlattice (SLS) long-wave infrared (LWIR) detector are investigated so that it operates at a lower bias voltage with lower dark current and higher photo response. At typical operating temperatures ( T ∼ 77 K), the dark current of GaSb/InAs SLS LWIR detectors is dominated by the Shockley–Read–Hall (SRH) generation–recombination (g–r) process in the space-charge (depletion) region. In order to suppress this dark current, a wide bandgap region next to the absorber layer has been included in recent SLS designs. A series of heterojunction-based LWIR SLS detectors with various doping and barrier profiles have been designed and characterized. The significance of the doping profile and thickness of the wide-bandgap layer in optimization of the heterojunction-based SLS detector performance are exhibited from the modeling and experimental results of these devices.

This paper correlates measurements of minority carrier lifetime using photoconductivity transient or photoconductive decay (PCD) with measurements and analysis of current–voltage (I–V) on P + n photodiodes of the same layer. This analysis is done at the primary temperature of operation near 77 K. Measurements of minority carrier lifetime in n-type molecular beam epitaxy Hg1−x Cd x Te (MCT) on variable substrates of GaAs and CdZnTe are presented. The minority carrier lifetime from I–V analysis of P + n long-wave infrared (LWIR) photodiodes on CdZnTe (CZT) and GaAs substrates is similar to PCD analysis. Deviations occur for MCT/GaAs in the low-temperature extrinsic region associated with Shockley–Read–Hall (SRH) at 78 K in contrast to MCT/CZT at similar temperatures. The x-values in the formula Hg1−x Cd x Te for samples grown on CdZnTe and GaAs are 0.22 and 0.235, respectively. I–V analysis of variable-area LWIR photodiodes shows a calculated minority carrier diffusion coefficient of 2.3 cm2/s on lattice-matched CZT and 3 cm2/s on non-lattice-matched GaAs with diffusion lengths of approximately 24 μm and 20 μm, respectively.

Reduction of threading dislocation density is critical for improving the performance of HgCdTe detectors on lattice-mismatched alternative substrates such as Si. CdTe buffer layers grown by molecular beam epitaxy (MBE), with thicknesses on the order of 8 μm to 12 μm, have helped reduce dislocation densities in HgCdTe layers. In this study, the reduction of threading dislocation densities in CdTe buffer layers grown on locally thinned Si substrates was examined. A novel Si back-thinning technique was developed that maintained an epiready front surface and achieved Si thicknesses as low as 1.9 μm. Threading dislocation densities, acquired by defect decoration techniques, were reduced by as much as 60% for CdTe buffer layers grown on these thinned regions when compared with unthinned regions. However, this reduction is inconsistent with prior notions that threading dislocation propagation is dominated by image forces. Instead, the thickness gradient of thinned Si may play a larger role.

This paper will discuss the desired quantum efficiency and dark current density of type-II strained-layer superlattice detectors (T2SLS), and required read-noise levels for long-wavelength infrared (LWIR) imaging applications at various background levels. The computation begins with noise equivalent irradiance NEI requirements with the focal plane array (FPA) operating at near-background limited infrared photodetection (BLIP) performance conditions. The paper will theoretically analyze the quantum efficiency and the dark current based on various components such as: diffusion, generation–recombination and tunneling, and dependence on the minority carrier lifetime of T2SL detector material. These calculations show appropriate minority carrier lifetime of the detector material for the various flux levels discussed in the article.

HgCdTe heteroepitaxy on low-cost, large-lattice-mismatched substrates such as Si continue to be plagued by large threading dislocation densities that ultimately reduce the operability of the thermal imaging detector array. Molecular-beam epitaxy (MBE) of 10 μm- to 15 μm-thick CdTe buffer layers has played a crucial role in reducing dislocation densities to current state-of-the-art levels. Herein, we examine the possibility that growth on locally back-thinned substrates could prove advantageous in further reducing dislocation densities in the CdTe/Si heteroepitaxial system. Using defect decoration techniques, a decrease in dislocation (etch-pit) density of up to ~42% has been measured in CdTe regions where the underlying Si substrate was chemically back-thinned to ~20 μm. A theoretical understanding is proposed, where a substrate-thickness-dependent dislocation image force is a likely cause for the experimentally observed reduction in threading dislocation density. These observations raise the prospect of combining localized substrate thinning with other techniques to further reduce dislocation densities to levels sought for HgCdTe/CdTe/Si and other large-lattice-mismatched systems.

Large-area high-quality Hg 1-x Cd x Te sensing layers for infrared imaging in the 8 μm to 12 μm spectral region are typically grown on bulk Cd 1-x Zn x Te substrates. Alternatively, epitaxial CdTe grown on Si or Ge has been used as a buffer layer for high-quality epitaxial HgCdTe growth. In this paper, x-ray topographs and rocking-curve full-width at half-maximum (FWHM) data will be presented for recent high-quality bulk CdZnTe grown by the vertical gradient freeze (VGF) method, previous bulk CdZnTe grown by the vertical Bridgman technique, epitaxial CdTe buffer layers on Si and Ge, and a HgCdTe layer epitaxially grown on bulk VGF CdZnTe.

It is well known that the large lattice mismatch (>14%) associated with CdTe/Si, CdTe/Ge, and CdTe/GaAs composite substrates, is a great contributor to large dislocation densities and other defects that limit the performance of HgCdTe-based infrared detectors. Though thermal expansion mismatch is another possible contributor to material defects, little work has been done towards documenting and understanding its effects in these systems. Here, we perform studies to determine the relative contributions of lattice and thermal mismatch to CdTe film characteristics, including dislocation density and residual stress. Unannealed and thermally cycled films are characterized using x-ray diffraction, defect decoration, and Nomarski and transmission electron microscopy. For CdTe/Si, the residual stress is consistently observed to be tensile, while for CdTe/Ge and CdTe/GaAs, a compressive residual film stress is measured. We show based on theoretically predicted stress levels that the experimental measurements imply the dominance of thermal mismatch in the residual stress characteristics.

We report on the significance of thermal expansion mismatch in the heteroepitaxial growth of CdTe on highly lattice-mismatched substrates. Such substrates including Si, Ge, or GaAs are desirable for CdTe buffer layer growth and subsequent deposition of HgCdTe infrared absorber layers. Besides lattice misfit, the thermal mismatch associated with these systems can produce additional strain and defects at low or elevated temperatures. However, little work has been done towards documenting and understanding these effects. Experimental evidence of thermal-expansion-dependent residual stress is presented for CdTe/Si(2 1 1), CdTe/Ge(2 1 1), and CdTe/GaAs(2 1 1) films based on X-ray diffraction studies. The experimental results are also compared with residual stress calculations based on known material properties. These results may play a vital role in the design and development of HgCdTe detectors for large-format, infrared focal plane arrays (FPA).

Mid wave infrared (MWIR) imaging in the 3-5 um spectral band has traditionally been performed by InSb sensors. InSb technology is presently limited to a near 80K operating temperature and the hunt has been on for a higher operating temperature (HOT) technology that does as well at 150K as InSb at 80K, but with reduced power requirements. Amongst these alternative technologies are photovoltaic sensors consisting of heterostructures of HgCdTe (MCT). In previous work we assessed the device performance of several alternative MWIR HOT technologies (MCT on Si, MCT on GaAs) as a function of operating temperature. In this work we compare the NEDT histograms for these alternative technologies with InSb to better understand how their performance can be improved at higher temperatures. We also present analysis formalism for quantitatively assessing the number of FPA pixels which reside in the central versus the shoulder portions of the histogram.Begin the Introduction two lines below the Keywords. The manuscript should not have headers, footers, or page numbers. It should be in a onecolumn format. References are often noted in the text1 and cited at the end of the paper.

Well recognized are the potential benefits in camera simplicity, power reduction and increased cooler life associated with the capability of operating infrared focal plane arrays at or near room ambient temperatures. Quality imagery in the 3 to 5 mm spectral band at scene temperature of 300K with focal plane array temperatures up to 175K was demonstrated recently. The array consisted of 640*512, 16 mm pitch N+p(As) detector elements grown by metal organic vapor phase epitaxy on a GaAs substrate. In this paper, a carrier recombination model is presented that explains the dark current density data as a function of inverse temperature. Basically the dominant carrier recombination occurs through ionized donor-like flaws centered in the upper half of the energy gap. For Hg1-xCd x Te, x=0.3 and 0.2867 materials, the flaw energy level, Eflaw(0K) respectively, is centered at 0.189 eV and 0.1181 eV above the valence band edge; The shortest possible lifetime tp0 for hole capture respectively is 3.5 and 550 ms. Band to band recombination is not observed to be dominant even in the temperature region T a 300K, where the radiative and Auger lifetimes are significantly smaller than tp0. The asymmetry parameter g = tn0/tp0 ll1.© (2012) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.

Reported is a detailed analysis of the dark current versus voltage versus temperature data of planar hetero-structure P + n mid wavelength infrared MWIR photodiodes with band gap energy E g (78K) = 0.243 eV, λ g = 5.1 μm and long wavelength infrared LWIR photodiodes with E g (78K) = 0.115 eV, λ g = 10.8 μm. The purpose of the investigations is to identify the dominant carrier recombination mechanisms and in particular to determine at what temperature and voltage is the onset of Shockley Read Hall (SRH) space charge currents. The important finding is that the currents can mostly be explained by a combination of Auger (e-e) and radiative carrier recombination processes with no evidence of SRH recombination through near mid-gap states; a lower bound estimate of the SRH lifetime for LWIR photodiode is 100 μs. Intrinsic radiative recombination is found to be the dominant carrier recombination mechanisms for the MWIR photodiode with a carrier concentration N d =10 15 cm -3 , and Auger (e-e) being dominant for the LWIR photodiode. The LWIR Auger (e-e) lifetime data is well fitted with the Beattie, Landsberg and Blakemore (BLB) formulas with a constant overlap integral F1F2= 0.15, which is in accord with recent electronic band structure calculations. From the analysis of variable area LWIR photodiodes the minority carrier conductivity mobility and diffusion length at 80K are calculated to be 350 cm 2 /V-s and 23 μm respectively. The LWIR lifetime measured by the photoconductive decay method is in agreement with the expected intrinsic Auger (e-e) lifetime ≈ 2 μs at 80K and with the lifetimes obtained from device analysis. For T ≤ 40K, trap assisted tunneling is the dominant current in reversed bias LWIR photodiodes; forward bias currents are dominated by diffusion currents of origin in the n- layer. For the MWIR photodiode deviation from diffusion limited behavior to G-R is observed at T < 80K and, the SRH lifetimes ιn0 and ιp0 are estimated to be 50 ms. Measured and calculated external quantum efficiencies at the peak responsivity wavelength λpk for both MWIR and LWIR photodiodes are ≈ 70% at 78K. For imaging in the 3-5 μm spectral band scene temperature 300K, F/3 optics, the noise equivalent temperature difference NEuT of MWIR photodiodes is calculated to be near background limited performance BLIP =12.4 mK for detector temperatures Td ≤ 150K.

Superlattices composed of III–V heterostructures have established applications in high‐speed electronic and optoelectronic devices. As layer thicknesses are reduced, the role of heterostructure interface sharpness becomes more critical to ensuring high quality two‐dimensional growth. In this work, short‐period (less than 1 nm) superlattices with active layer thicknesses of 31 nm were investigated to assess interface roughness in the initial stages of growth. X‐ray diffraction was used to evaluate interface roughness and to calculate superlattice periodicity. Results suggest that surface roughening by islanding may be promoted by GaAs buffer layers that are 10–100 nm thick. Smoother interfaces were obtained in samples with buffer layers 250 nm and greater.

Superlattices composed of aluminum, gallium and indium are currently employed in a variety of device-related applications. Among these are edge-emitting GRINSCH lasers and vertical cavity surface emitting laser diodes. As the individual layer thickness is reduced, the role of interface sharpness becomes more critical in ensuring good two-dimensional growth. This work addresses the relationship between interface roughness and superlattice crystallinity for short-period AlAs/GaAs superlattices. Thin short-period superlattices with active layer thicknesses of 30 nm or less were also investigated to help determine the interface sharpness in the initial stages of growth. X-ray diffraction was used to assess interface roughness and to calculate superlattice periodicity. These results are compared with those obtained by reflection high energy electron diffraction (RHEED), Raman spectroscopy, and spectroscopic ellipsometry. The results indicate that interface roughness is promoted by a reduced arsenic flux growth condition at normal growth temperatures for short-period superlattices. The results also suggest that, for thin superlattices, a 10 nm buffer layer enhances interface roughness in the initial stages of growth and compromises the subsequent epilayer crystallinity. An analysis of these results in the light of structural, dynamical, and optical data is presented.

In this work the current versus voltage data of a p-n+ junction is converted into minority carrier lifetime data. Space charge recombination currents dominate at modest reverse bias at 80K and taking the dominant recombination centers to be located at the intrinsic Fermi level, the lowest minority carrier lifetime τ0 is determined to be 35ns. This single Shockley-Read-Hall carrier recombination parameter provides an excellent fit to the data over temperature range 40K≤ T≤ 130K; the 35ns minority carrier lifetime also explains the quantum efficiency data. The transition from diffusion to space charge currents occurs for temperatures, T ≤ 100K. For T≤ 40K trap assisted tunneling is the dominant current component. Based on imaging system requirements to be near background limited for photon flux ≈ 1015 ph/cm2-s and detector temperature of 80K, the minority carrier lifetime will need to be increased by one order of magnitude.

The dramatically different and superior properties of molecular beam epitaxy (MBE) of silicon on sapphire (SOS) have been investigated and compared with standard commercially available chemically vapor deposition (CVD) SOS. X-ray diffraction reveals a 24% reduction in the strain of the MBE SOS relative to the CVD SOS. The MBE SOS has a 40% higher electron Hall mobility at room temperature. At liquid N 2 temperatures, the electron Hall mobility of the MBE SOS increases instead of decreasing as in CVD SOS. The microtwin differential volume fraction profile for MBE SOS is lower by more than an order of magnitude compared with that of CVD SOS; it decreases faster with distance from the Si-sapphire interface; and it effectively goes to zero at 0.3 μm from the interface. The average Si-sapphire interface charge for MBE SOS is −8.0×10 10 cm −2 , which is negative and more than an order of magnitude lower than the interface charge of 2×10 12 cm −2 for CVD SOS. Some of the unique features of the Naval Research Laboratory VG80 Si MBE/Surface-Analytical System are discussed.

The existence of both the strain and microroughness at the interface of thermally grown SiO2 films on Si was ascertained unambiguously for the first time by high accuracy spectroscopic ellipsometry. The dielectric function of the interface was determined by a comprehensive data analysis procedure. By carefully examining the dielectric function obtained by our model, the strain was seen to cause a red shift of 0.042 eV of the interband critical point E1 compared with the bulk silicon value. The thickness of the interface region was found to be 2.2 nm of which a significant part is due to the strain.

Suppression of generation-recombination dark current and bias stability in long wavelength infrared (LWIR) strained layer superlattice (SLS) detectors, consisting of a lightly doped p-type absorber layer and a wide bandgap hole barrier, are investigated with respect to the wide bandgap barrier layer thickness and doping profile. Dark current IV, photoresponse, and theoretical modeling are used to correlate device performance with the widegap barrier design parameters. Decreased dark current density and increased operating bias were observed as the barrier thickness was increased. This study also identifies key device parameters responsible for optimal performance of heterojunction based SLS LWIR detector.

Techniques based on optical, x ray, and electron microscopy measurements are applied to characterized a wide variety of semiconductor multilayer structures. Bragg mirrors serve as valuable test structures for evaluating the epitaxial uniformity of crystal growth systems. Careful characterization of half-wave space single quantum wells provides a method for determining their complex refractive indices using reflectance spectroscopy. Comparison of cross-sectional microphotoluminescence to surface-normal photoluminescence, combined with these characterization techniques, allows studies of spontaneous emission in microcavities and elucidates the difficulties with using surface-normal photoluminescence to determine the alloy composition of the mirror layers. The application of these characterization methods to visible- wavelength AlGaAs mirrors, 485-720 nm, enables the development of these mirrors for uses such as optically tailored substrates and visible surface-emitter or detector arrays.© (1994) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

Theoretical modeling and experimental evidence show that the dark currents of antimonide (Sb)-based Type-II Superlattice (T2SL) detectors sensitive to long-wavelength infrared (LWIR) radiation are limited by the minority carrier lifetimes associated with the Shockley Read-Hall (SRH) generation-recombination process. Despite the low minority carrier lifetimes, the present photodiode dark current performance is achieved by increasing the background doping density of the absorber layers to NA ∼ 2×1016 cm−3. This paper will discuss the measured minority carrier lifetimes of T2SL LWIR detectors with various background doping densities. To make comparisons, we designed several T2SL absorber layers sensitive in the LWIR range and p-type doped up to various densities. We find the minority carrier lifetimes are dominated by the SRH generation-recombination process. By analyzing minority carrier lifetime data as a function of excess carrier densities, we estimate SRH lifetimes and actual ionized acceptor densities of the absorber layers. The data are compared with the measured impurity doping densities of the detectors. In addition, we predict the type of flaws responsible for the SRH recombination process and narrow down the flaw energy level relative to the Fermi energy.

Threading dislocations are a significant problem for heteroepitaxial growth of thin films on large lattice-mismatched substrates. In the case of HgCdTe thin films on Si, Ge, or GaAs, the molecular beam epitaxy (MBE) of 10–15-μm-thick CdTe buffer layers has historically played a crucial role in reducing threading dislocation densities to current state-of-the-art levels. In this work, the authors investigate a localized substrate thinning approach and its overall effect on further reducing dislocation densities in the CdTe/Si heteroepitaxial system. In using substrates with regions thinned to thicknesses on the order of the CdTe buffer, the attempt is to reduce the dislocation image force acting from the interface toward the epilayer surface. The authors employ both wet- and dry-etching techniques to create locally back-thinned regions of Si(211) wafers. Localized rather than whole wafer thinning was necessary to maintain sufficient substrate thickness for handling. The opposite sides of the wafers were cleaned using standard techniques prior to CdTe MBE. Scanning electron microscopy and Fourier transform infrared spectroscopy were used to measure epilayer and substrate thicknesses. Using CdTe defect-decoration techniques, a decrease in threading dislocation density by up to 60% has been observed in regions for which the underlying Si substrate was thinned to 2 μm. Results obtained for wet-etch and dry-etch back-thinning approaches suggest that the dislocation-reduction mechanism is not solely based on substrate-thickness induced image forces.Threading dislocations are a significant problem for heteroepitaxial growth of thin films on large lattice-mismatched substrates. In the case of HgCdTe thin films on Si, Ge, or GaAs, the molecular beam epitaxy (MBE) of 10–15-μm-thick CdTe buffer layers has historically played a crucial role in reducing threading dislocation densities to current state-of-the-art levels. In this work, the authors investigate a localized substrate thinning approach and its overall effect on further reducing dislocation densities in the CdTe/Si heteroepitaxial system. In using substrates with regions thinned to thicknesses on the order of the CdTe buffer, the attempt is to reduce the dislocation image force acting from the interface toward the epilayer surface. The authors employ both wet- and dry-etching techniques to create locally back-thinned regions of Si(211) wafers. Localized rather than whole wafer thinning was necessary to maintain sufficient substrate thickness for handling. The opposite sides of the wafers were cle...

We present comparisons of photoluminescence (PL) data for various vertical-cavity surface-emitting laser (VCSEL) and distributed quantum well structures taken with the pump beam (and the collection path) in two different configurations: normal to the surface of the sample; and perpendicular to a cross-section of the epitaxial layers. We demonstrate that the cross-sectional PL (XPL) technique can resolve individual features in the structures, and that the surface-normal PL (NPL) spectra are perturbed by the multilayer mirrors in the VCSELs. We elucidate a potential method for transforming between the NPL spectra and the non-perturbed XPL spectra and evaluate the sensitivity of this method to various measurement as well as material parameters. This simulation technique is well-suited to wide parametric variations of the dispersion curves for the complex dielectric constant of the materials, the pump field distribution, and the depth profile of the gain medium.

Simulations of reflectance spectra and electric field distributions for vertical-cavity structures were used in the computer aided design of epitaxial mirrors and lasers. The binary GaAs/AlAs superlattice alloys and AlxGa1−xAs random alloys that compose these structures were grown by molecular beam epitaxy. Photoluminescence, photoreflectance, reflectance spectroscopy, scanning electron microscopy, transmission electron microscopy, and double crystal x-ray diffractometry were applied to characterize cavity and Bragg mirror layer thicknesses and alloy composition.

Photoreflectance (PR) was used to study crystalline quality and stress in silicon films on insulator. The position and amplitude of the 3.4 eV PR silicon structure was monitored for both MBE silicon on sapphire (SOS) and SIMOX structures. The SOS film thicknesses ranged from 6 to 4000 nm. The shift in energy of the 3.4 eV structure from its bulk position is dependent on the sample thickness and on the strain in the films. In the SIMOX case, the amplitude of the 3.4 eV PR signal provided information about the crystalline quality of the top silicon layer for a set of six samples, each one removed at a different step of a process involving three implantation-anneal cycles. In this case the PR signal appeared to deteriorate with the each cycle undergone by the samples. Further investigations are needed to resolve the discrepancy bet ween these SOS results and the ones obtained in an earlier set of measurements.

The effects of temperature overshoot during molecular beam epitaxy growth on the transport properties of conventionally and delta-doped pseudomorphic high electron mobility transistor (pHEMT) structures have been examined. A diffuse reflectance spectroscopy (DRS)-controlled versus a thermocouple (TC)-controlled, growth scheme is compared. Several advantages of the DRS-grown pHEMTs over the TC-controlled version were observed. Modest improvements in mobility, on the order of 2%–3%, were observed in addition to a 20% reduction in carrier freeze-out for the DRS-grown pHEMTs at 77K.

We report the use of diffuse reflectance spectroscopy for active, closed-loop control of substrate temperature during the growth of a modulation doped heterostructure. Measurement and control of substrate temperature is a common difficulty for molecular beam epitaxy (MBE), as well as other semiconductor deposition techniques. To examine the effect of the temperature lag experienced during conventional MBE, we have grown identical pairs of GaAs/InGaAs/AlGaAs pseudomorphic high electron mobility transistors (pHEMTs). For one pHEMT in each pair, the input signal for substrate temperature control was the standard thermocouple (TC); for the other, it was diffuse reflectance spectroscopy (DRS). Under TC control, an overshoot of up to 70 °C was observed during the temperature upramp following the lower-temperature deposition of the InGaAs layer. This overshoot was eliminated under DRS control. Temperature errors can lead to heterolayer changes such as segregation, desorption, and changes in dopant activation.

Using transmission electron microscopy, we have examined a number of (001) silicon thin films grown on (1012) sapphire substrates by molecular beam epitaxy (MBE). We have found that for silicon films less than 0.55 μm thick, microtwins are very much in evidence. For silicon films greater than 700 nm thick, however, dislocations, rather than microtwins, are the predominant defect. It is our conjecture that dislocation extension, and the associated disappearance of microtwins in thicker MBE‐grown SOS films, is analogous to the generation of misfit dislocations in silicon‐germanium films grown on silicon or germanium substrates by MBE; furthermore, these observations can be understood via the concept of excess stress that has been recently formulated by Tsao, Dodson, and others. The persistence of microtwins in SOS grown by chemical vapor deposition, as opposed to MBE‐grown SOS, can be understood in terms of Dodson and Tsao’s formulation of plastic deformation kinetics in thin films.

An x-ray diffraction study is made of the effect of silicon film thickness on the peak broadening associated with the (024) sapphire Bragg reflection peak for MBE—grown SOS material. The predeposition treatment and growth parameters for the samples in the series were identical. The thicknesses ranged from 5500 to 40,000 angstroms and the growth rate was roughly I angstrom/second.SOS films with silicon thicknesses below 5500A did not produce sapphire peak broadening when compared with the corresponding sapphire standard. With reference to standard sapphire reflection peaks, the 5500A film shows slight broadening while a I micron film broadened 14 seconds of arc when compared at FWHM with the sapphire standard. A possible explanation for this is that at overlayers less than 5500A, the film is not sufficiently massive to exert a uniform strain on the sapphire. At 5500A the film attains a critical thickness sufficient to strain the substrate and produce detectable broadening. For thickerfilms the strain would increase proportionally. Results from lattice parameter measurements on the silicon epilayer indicate that the perpendicular lattice parameter relaxes atgreater thicknesses but is still in tension when compared with bulk silicon. One would expect that the strain gradient suggested by these results would be greatest at the silicon/sapphire interface and that the defect concentration at the interface might beaffected by this strained condition.

We have continued our investigation1 of the effects of pre—deposition substrate annealing for the case of MBE grown silicon on sapphire. Three identical series of samples were grown with film thicknesses ranging between 65 and 1500 angstroms. Each series of samples was grown upon sapphire which had been annealed at either 1450ºC, 1300ºC, or 900ºC. The growth temperature and growth rate were the same for each series. The anneal time for each sample was 30 minutes.

Beryllium is an effective p-dopant in GaAs and AlGaAs and plays an important role in device characterizations of hetero bipolar transistors. This work addresses the doping and mobility properties for two series of beryllium-doped samples: GaAs and AlGaAs. Within each series the doping ranged between 3×1015cm-3 to levels of 5×1019cm-3. Mobility and carrier concentrations were obtained through Hall and Polaron measurements. The doping concentration results suggest the onset of carrier compensation at higher doping levels. One possible explanation is that for high doping levels, Be is incorporated as interstitial donors. A thermodynamic model is used to explain the observations.

To explore the role of interface scattering in high electron mobility transistor (HEMT) device performance, a series of samples consisting of both a superlattice and a HEMT structure were grown by molecular beam epitaxy (MBE) at temperatures ranging from 500 to 630 °C. Hall measurements indicate a trend toward higher mobilities in samples grown at higher temperatures. Subsequent x‐ray reflectivity measurements were made, and the data were fitted by least‐squares refinement of a calculated reflectivity curve determined from a model of the sample structure to obtain the composition profile along the growth direction. These results indicate smoother interfaces for the samples with higher mobilities.