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As the semiconductor industry continues pushing Moore’s law to the next node, interconnect structures scaling will be a key element to performance improvement of functional devices. However, the requirements for low LCDU and defectivity of these interconnect structures have become more stringent with continuous scaling. In this paper, a fundamental study is conducted to understand the impact of various factors on the patterning of EUV single exposure vias, and to find effective strategies to shrink CD while improving LCDU and defectivity. The work is based on a 40 nm pitch orthogonal via array baseline, and probes different patterning factors including illumination, resist materials, stack, scanner, and develop methods for LCDU improvement and defectivity reduction. The patterns are transferred to bottom dielectrics to study the evolution of LCDU and defectivity during etching.

Successful pattern transfer from the photoresist into the substrate depends on robust layers of lithographic films. Typically, an alternating sequence of inorganic (most often Si containing) and organic hardmask (HM) materials is used. Pattern transfer occurs then by using reactive ion etch (RIE) chemistry that is selective to one particular layer (such as: flurorinated RIE for Si HM). The impact of these RIE gases onto the layers acting as hardmask for the layer to be etched is typically neglected, except for known sputtering effects. We found that components of the RIE gases can penetrate deep into the “inert” layers and significantly modify them. For example, nitrogen used as component to etch spin-on carbon layers was found to travel up to 70 nm deep into Si HM materials and create layers with different material properties within this film. The question is being raised and discussed to which extent this atom implantation may impact the pattern transfer of the ever shrinking features.

Initial readiness of EUV (extreme ultraviolet) patterning was demonstrated in 2016 with IBM Alliance's 7nm device technology. The focus has now shifted to driving the 'effective' k1 factor and enabling the second generation of EUV patterning. With the substantial cost of EUV exposure there is significant interest in extending the capability to do single exposure patterning with EUV. To enable this, emphasis must be placed on the aspect ratios, adhesion, defectivity reduction, etch selectivity, and imaging control of the whole patterning process. Innovations in resist materials and processes must be included to realize the full entitlement of EUV lithography at 0.33NA. In addition, enhancements in the patterning process to enable good defectivity, lithographic process window, and post etch pattern fidelity are also required. Through this work, the fundamental material challenges in driving down the effective k1 factor will be highlighted.

A spin-on organic Graded Bottom AntiReflective Coating (GBARC) was developed to enable appropriate reflectivity control during advanced photoresist patterning using 193nm immersion lithography up to 1.35 NA (limits of hyper-NA lithography using water as immersion fluid). This novel technology constitutes a simplified reflectivity control approach over more conventional schemes such as dual-layer BARCs, trilayer stacks or single layer BARCs. The GBARC layer is formed upon vertical phase separation of optically tuned polymeric components present in a GBARC casting solution during the spin-coating and post-applied baking steps. The substrate surface energy is found to dictate the direction of the spatial assembly for any given phase-separating polymer blend combination. The index of refraction (n193) of the GBARC polymeric components is approximately matched to that of the photoresist and substrate layers for optimum reflectivity control, while the extinction coefficient (k193) increases gradually towards the substrate. Analytical characterization of the varying optical constants throughout the GBARC film is achieved by Variable Angle Spectroscopic Ellipsometry (VASE) which allows for a quantitative description of the optical gradient present within the GBARC layer. The optical gradient sharpness is shown to be impervious to total GBARC thickness variations at constant relative polymer mass loading as well as changes in the relative mass loading of polymeric components at fixed total GBARC thickness. Also, the link between image profile afforded by various levels of reflectivity control and the mechanical stability of photoresist nanostructures is investigated at 1.2NA by designing GBARC formulations with variable residual reflectivity. Substrate reflectivity in excess of 1% is shown to limit the focus-exposure window due to pattern collapse. Last, adhesion of 193 nm photoresist patterns to a GBARC film is compared to a commercially available single layer BARC. Enhanced adhesion is demonstrated in the case of the GBARC surface, despite the low surface energy that typifies GBARC layers

During exposure in an EUV scanner, photoresist and other materials coated on a wafer are known to outgas various species. As a requirement to pattern materials in an ASML NXE scanner, these materials need to be screened for outgassing and possible optics contamination. As part of the testing process, a resist-coated wafer is exposed in a vacuum chamber mimicking the conditions inside an EUV scanner. The resist exposure source can be either EUV photons or electron beam (e-beam). This presentation will cover the results to date on a SEMATECH program to study resist outgassing from both the commercial system from EUV Tech and a custom Resist Outgassing and Exposure (ROX) tool. The EUV Tech results reported will be based on electron exposures of the photoresist, and the ROX results reported will be based on EUV photon exposures of the photoresist. The results reported will cover both tools and the measurements of over 80 commercial photoresists.

Traditional patterning stacks for deep ultraviolet patterning have been based on a trilayer scheme with an organic planarizing layer, silicon antireflective coating or organic bottom antireflective coating, and photoresist. At an extreme ultraviolet (EUV) wavelength, there is no longer a need for reflectivity control. This offers an opportunity to look at different types of underlayers for patterning at sub-36 nm pitch length scales. An alternate hardmask can be used to develop a low aspect ratio patterning stack that can enable a larger process window at sub-36 nm pitch resolution. The hardmask layer under the resist has the potential for secondary electron generation at the resist/hardmask interface to improve resist sensitivity. This work explores EUV patterning on deposited hardmasks of various types such as silicon oxides and metal hardmasks. It also details the challenges of patterning directly on an alternate underlayer and approaches for improving patterning performance on such layers.

The first use of extreme ultraviolet (EUV) lithography in logic manufacturing is targeted for the 14 nm node, with possible earlier application to 20-nm node logic device back-end layers to demonstrate the technology. Use of EUV lithography to pattern the via-levels will allow the use of dark-field EUV masks with low pattern densities and will postpone the day when completely defect-free EUV mask blanks are needed. The quality of the imaging at the 14 nm node with EUV lithography is considerably higher than with double-dipole or double-exposure double-etch 193-nm immersion lithography, particularly for 2-dimensional patterns such as vias, because the Rayleigh k 1 -value when printing with 0.25 numerical aperture (NA) EUV lithography is so much higher than with 1.35 NA 193-nm immersion lithography and the process windows with EUV lithography are huge. In this paper, the status of EUV lithography technology as seen from an end-user perspective is summarized and the current values of the most important metrics for each of the critical elements of the technology are compared to the values needed for the insertion of EUVL into production at the 14 nm technology node.

Fully functional 512Kb static-random access memory (SRAM) devices containing more than 3.6 million transistors have been successfully fabricated in a 0.25 μm complementary metal oxide semiconductor (CMOS) technology using compact storage ring X-ray lithography thus demonstrating the functionality of the X-ray lithography infrastructure. A lithographic performance comparison was made between x-ray lithography and optical (excimer laser) lithography by fabricating SRAM devices using both lithographic techniques. The excellent process latitude and dimension control available for x-ray lithography is reflected in this comparison. A comprehensive discussion of the advantages of x-ray lithography is discussed in this paper.

Spin-on underlayers are currently being employed by the lithographic industry to improve the imaging performance of EUV resists. In this work, multiple examples have shown improved line-edge roughness (LER) of an open-source resist using new open-source underlayers in comparison to a primed silicon substrate. Additionally, several experiments demonstrate better resist adhesion on underlayers that have lower coefficients of thermal expansion (CTE). Both organic and inorganic underlayers provide better resist LER when their CTE is lower.

Underlayers (UL), such as organic planarizing layers (OPLs) or spin-on carbon (SOC) layers, play a very important role in various integration schemes of chip manufacturing. One function of OPLs is to fill in pre-existing patterns on the substrate, such as previously patterned vias, to enable lithographic patterning of the next level. More importantly, OPL resistance to reactive ion etch (RIE) processes used to etch silicon-containing materials is essential for the successful pattern transfer from the resist into the substrate. Typically, the pattern is first transferred into the OPL through a two-step RIE sequence, followed by the transfer into the substrate by a fluorine-containing RIE step that leaves the OPL pattern mainly intact. However, when the line/space patterns are scaled down to line widths below 35 nm, it was found that this last RIE step induces severe pattern deformation ("wiggling") of the OPL material, which ultimately prevents the successful pattern transfer into the substrate. In this work, we developed an efficient process to evaluate OPL materials with respect to their pattern transfer performance. This allowed us to systematically study material, substrate and etch process parameters and draw conclusions about how changes in these parameters may improve the overall pattern transfer margin.

In this work, we investigate the Negative Tone Develop (NTD) process from a fundamental materials/process interaction perspective. Several key differences exist between a negative tone develop process and a traditional positive tone develop system. For example, the organic solvent dissolves the unexposed material, while the deprotected resist remains intact. This causes key differences in key patterning properties, such as pattern collapse, adhesion, remaining resist, and photoresist etch selectivity. We have carried out fundamental studies to understand these new interactions between developer and remaining resist with negative tone develop systems. We have characterized the dynamic dissolution behavior of a model system with a quartz crystal microbalance with both positive and negative tone solvent developers. We have also compared contrast curves, and a fundamental model of image collapse. In addition, we present first results on Optical Proximity Correction (OPC) modeling results of current Negative Tone Develop (NTD) resist/developer systems.

Pitch-split resist materials have been developed for the fabrication of sub-74 nm pitch semiconductor devices. A thermal cure method is used to enable patterning of a second layer of resist over the initially formed layer. Process window, critical dimension uniformity, defectivity and integration with fabricator applications have been explored. A tone inversion process has been developed to enable the application of pitch split to dark field applications in addition to standard bright field applications.

Pitch doubling technologies are necessary for the 32nm half-pitch (HP) and beyond in order to extend optical lithography. Many different techniques have been examined including Litho-Litho-Etch (LLE), Litho-Etch, Litho-Etch (LELE), and Sidewall Image Transfer (SIT). Keeping all of the processes inside the litho cluster, as LLE achieves, affords process simplification and potential for the lowest cost of ownership for pitch doubling. Within LLE alone, there are varying approaches including spin-on chemical freeze materials, thermal cure, UV curable materials, among others. The challenge is to provide robust process performance while still achieving the lowest cost of ownership. For this paper, we are concentrating on the evaluation of the UV cure process. Our findings are the results of optimization of the UV cure dose and bake conditions and its affect on the lithographic performance. The optimized process was investigated for defectivity, critical dimension (CD), repeatability, pattern distortion, etch performance and readiness for high volume manufacturing. With respect to CD, the investigation included absolute value change (shrinkage or growth) and CD uniformity (CDU). For pattern distortion, we investigated line shrinkage, corner rounding, and line end pull back. Defectivity checks were conducted for full wafer comparison pre and post the UV cure process. Manufacturability measures include throughput, cost of ownership and process stability.

Litho-Etch-Litho-Etch double patterning requires aggressive shrink of each sub-pattern's critical dimensions to enable inter-digitation and pitch doubling. Application of this double patterning technique to elliptical contacts introduces a new constraint to the CD shrink processes as controlling the 2-D aspect ratio of elliptical contacts is critical for both device performance and yield. The impact of a track-applied chemical shrink and reactive ion etch [RIE] shrink processes to pre/post RIE 2-D aspect ratios [2-D AR] have been evaluated. A methodology for controlling 2-D aspect ratios with an aggressive CD shrink target is described using a 2:1 aspect ratio test pattern resulting in the successful fabrication of 2:1 aspect ratio bottom CD contacts with 65% bias from the lithographic CD.

We are evaluating the readiness of extreme ultraviolet (EUV) lithography for insertion into production at the 15 nm technology node by integrating it into standard semiconductor process flows because we believe that device integration exercises provide the truest test of technology readiness and, at the same time, highlight the remaining critical issues. In this paper, we describe the use of EUV lithography with the 0.25 NA Alpha Demo Tool (ADT) to pattern the contact and first interconnect levels of a large (~24 mm x 32 mm) 22 nm node test chip using EUV masks with state-of-the-art defectivity (~0.3 defects/cm2). We have found that: 1) the quality of EUVL printing at the 22 nm node is considerably higher than the printing produced with 193 nm immersion lithography; 2) printing at the 22 nm node with EUV lithography results in higher yield than double exposure double-etch 193i lithography; and 3) EUV lithography with the 0.25 NA ADT is capable of supporting some early device development work at the 15 nm technology node.

We used Cu contact metallization to solve one of the critical challenges for 22 nm node technology. Cu contact metallization allowed us to demonstrate world's smallest and fully functional 22 nm node 6T-SRAM [1]. Cu contact metallization was executed using CVD Ru-containing liner. We obtained early reliability data by thermally stressing bulk device. Bulk device parameters such as junction and gate leakage currents and overlap capacitance were stable after BEOL anneal stress. We also demonstrated the extendibility of Cu contact metallization using 15 nm contacts.

Spin-on chemical shrink, reactive ion etch [RIE] shrink and litho-etch-litho-etch [LELE] double patterning have been utilized to produce dense 90 nm pitch, 26 nm bottom CD contacts starting from 65 nm CD, 126 nm diagonal pitch as printed features. Demonstrated lithographic process window, post etch pattern fidelity, CD, and CD uniformity are all suitable to production. In addition, electrical test results shows a comparable defect a ratio vs. a no chemical shrink baseline.

On the road to insertion of extreme ultraviolet (EUV) lithography into production at the 16 nm technology node and below, we are testing its integration into standard semiconductor process flows for 22 nm node devices. In this paper, we describe the patternin g of two levels of a 22 nm node test ch ip using single-exposure EUV lithography; the other layers of the test chip were patterned using 193 nm immersion lithography. We designed a full-field EUV mask for contact and first interconnect le vels using rule-based corrections to co mpensate for the EUV specific effects of mask shadowing and imaging system flare. The resulting mask and the 0.25-NA EUV scanner utilized for the EUV lithography steps were found to provide more than adequate patterning performance for the 22 nm node devices. The CD uniformity across the exposure field and through a lot of wafers was approximately 6.1% (3V ) and the measured overlay on a representative test chip wafer was 13.0 nm (x) and 12.2 nm (y). A trilayer resist process that provided ample process latitude and sufficient etch selectivity for pattern transfer was utilized to pattern the contact and first interconnect levels. The etch recipes provided good CD control, profiles and end-point discrimination. The patterned integration wafers have been processed through metal deposition and polish at the contact level and are now being patterned at the first interconnect level. Keywords: Extreme ultraviolet lithography, EUVL, EUV device inte gration, EUV OPC, EUV mask, EUV resist process

Reticle defectivity was evaluated using two known approaches: direct reticle inspection and the inspection of the wafer prints. The primary test vehicle was a reticle with a design consisting of 45 nm and 60 nm comb and serpentine structures in different orientations. The reticle was inspected in reflected light on the KLA 587 in a die-todie and a die-to-database mode. Wafers were exposed on a 0.25 NA full-field EUV exposure tool and inspected on a KLA 2800. Both methods delivered two populations of defects which were correlated to identify coinciding detections and mismatches. In addition, reticle defects were reviewed using scanning electron microscopy (SEM) to assess the printability. Furthermore, some images of the defects found on the 45 nm reticle used in the previous study [1] were collected using actinic (EUV) microscopy. The results of the observed mask defects are presented and discussed together with a defect classification.

We demonstrate 22 nm node technology compatible, fully functional 0.1 mum2 6T-SRAM cell using high-NA immersion lithography and state-of-the-art 300 mm tooling. The cell exhibits a static noise margin (SNM) of 220 mV at Vdd=0.9 V. We also present a 0.09 mum2 cell with SNM of 160 mV at Vdd=0.9 V demonstrating the scalability of the design with the same layout. This is the world's smallest 6T-SRAM cell. Key enablers include band edge high-kappa metal gate stacks, transistors with 25 nm gate lengths, thin spacers, novel co-implants, advanced activation techniques, extremely thin silicide, and damascene copper contacts.

We have used ASML’s full field step-and-scan exposure tool for extreme ultraviolet lithography (EUVL), known as an Alpha Demo Tool, to investigate one of the critical issues identified for EUVL, defectivity associated with EUV masks. The main objective for this work was to investigate the infrastructure currently in place to examine defects on a EUV reticle and identify their consequence in exposed resist. Unlike many previous investigations this work looks at naturally occurring defects in a EUV exposed metal layer from a 45 nm node device. The EUV exposure was also integrated into a standard process flow where the other layers were patterned using more conventional 193-nm lithography techniques. This presentation correlates reticle level defectivity to resulting wafer exposures. Defect inspection data from both the 28xx family of KLA-Tencor wafer inspection tool and Terascan reticle inspection tools are presented. Defect populations were characterized with a KLA 5200 Review SEM. Observed defectivity modes were analyzed using both conventional defect inspection methodology as well as advanced techniques in order to gain further insight. We find good correlations between reticle level defects and the resulting wafer exposure defects.

The interaction of water with the photoresist film stack is proving to be a key factor in the current generation of 193-nm immersion lithography. Photoresist performance, CD control, optics lifetime, defectivity, overlay and possibly even tool throughput can all be affected by this interaction. Defect control has been an area of increasing concern as the source of the defects can be quite different than that found in conventional dry lithography [1]. Defects can originate from the UPW (Ultra Pure Water) either as particulates or as dissolved solids that precipitate from residual droplets left behind after scanning. Another source of defects can be particulates generated by the immersion fluid as it flows through the exposure tool or as a consequence of water contact with the resist film or resist/topcoat film stack. Recently there have been reports of printable defects due to stains or watermarks on the surface of the photoresist [2]. In this report we describe techniques for the visualization of watermarking and particulate formation on a variety of film surfaces. We also describe experiments testing the staining of a variety of water contaminants and additives and their effect on imaging performance. We will also describe the effect of different topcoats on imaging and defectivity in terms of their surface properties.

The mask fabrication industry is slowly migrating to chemically amplified (CA) resists to take the advantages of their high contrast, resolution, and sensitivity. During this migration process, the industry has encountered several problems associated with CA resists such as baking homogeneity of thick mask plates on hot plates, footing on Cr masks, and storage stability of mask blanks. In addressing these issues, we have adopted a low Ea CA resist platform to overcome the bake latitude issue. The resist formulation has been reformulated to reduce the footing and a new package method has bee introduced to extend the storage of the blanks. In addition, we will also discuss our studies on two major areas, such as sensitivity and etch resistance, which we think is extremely important for E-beam resists in the future. The mask industry started with 248nm DUV CA resist systems and then found out that there was a need for even higher sensitivity resist systems to address the throughput issue. In our early study, we have observed that by simply increasing photoacid generator loading in the resist formulation we were able to increase the sensitivity, but there was a significant reduction in the dose latitude. After studying the dissolution and inhibition properties of different PAGs, we have been able to optimize PAG and base loading in combination with proper choice of PAGs to achieve high sensitivity and large dose latitude. The new resist formulation exhibits a large dose latitude of 38% for 100 nm 1/s images with high sensitivity of 4.4μC/cm 2 at 100 kV. Due to the electron scattering effect and the image collapse issues with thicker resists, thinner imaging layer is desirable. Sufficient etch selectivity is needed to compensate the insufficient resist thickness. Therefore, there is a need to develop a high Cl 2 /O 2 RIE (used in Cr etch process) etch resistant resist system for mask making. We have reported earlier that a resist formulation based on blending KRS-XE with SSQ polymer has resolved 50nm 1/s resist images with etch rate 20% better than conventional novolak 1-line resist systems. Since then, we have investigated a few new SSQ polymers and found some lithographic improvement in this new blending systems due to better compatibility of the SSQ polymer to the KRS-XE.

While evaluating 193 nm, and early versions of 157 nm and EUV resists, the lithography community has focused on post-develop LER values derived from image analysis of top-down SEM micrographs. These numbers, however, do not capture the tendency of a resist to facet and roughen during plasma etching processes. They also do not convey any information about the role of the anti-reflective coatings/hard masks in the transfer of resist roughness into the underlying substrate. From a manufacturing perspective, it is the "LER" of the final etched substrate that is more important. This paper systematically studies the impact of resist polymer platform and thickness, etching conditions, and presence of organic and inorganic anti-reflective coatings/hard masks on substrate roughening. An AFM technique, previously developed by Reynolds and Taylor, is used to measure the feature sidewall roughness as a function of etch depth. This technique enables us to calculate the sidewall roughness of the resist, ARC/hard mak and substrate surfaces simultaneously, and determine correlations that may exist between these values. The paper identifies and demonstrates patterning methodologies that can be used to achieve "smooth" substrate surfaces even when the resist is "thin".

Line edge roughness (LER) has been widely perceived to be one of the roadblocks to the continuing scaling of semiconductor devices. However, little evidence has been published on the impact of LER on device performance, particularly on the performance and the reliability of advanced interconnects. In this paper, we present such evidence from both the Front-End-Of-Line (FEOL) and Back-End-Of-Line (BEOL) standpoints. In the FEOL, we employed computer simulations to estimate the effects of LER on a number of performance parameters of sub-100nm transistors based on 2-dimensional and 3-dimensional device models. LER has been shown to affect both the average value and the variance of key device performance parameters for sub-100nm transistors. In the BEOL, we investigated the impact of LER on the performance of barrier layers in dual damascene copper interconnects. To this end, we emulated LER by roughening Si surfaces with controlled patterning by self-assembled diblock copolymers and reactive ion etching. In-situ time-resolved X-ray diffraction was used to study Cu diffusion through about 5nm Ta and TaN barrier layers deposited by plasma enhanced-atomic layer deposition (PE-ALD) on both smooth and rough surfaces. The X-ray diffraction results indicated that the surface roughness does not degrade barrier performance of the ALD Cu barriers. Mechanism of the roughness effects is also discussed. Line edge roughness is, however, expected to degrade copper interconnect performance by increasing copper electrical resistivity through enhanced electron surface scattering.

A high-performance 0.25- mu m CMOS (complementary metal oxide semiconductor) technology with a reduced operating voltage of 2.5 V is presented. A loaded ring oscillator (NAND FI=FO=3. C/sub w/=0.2 pF) delay per stage of 280 ps achieved (W/sub eff//L/sub eff/=15 mu m/0.25 mu m), which is a 1.7 X improvement over 0.5- mu m CMOS technology. At shorter channel lengths (0.18 mu m), a CMOS stage delay of 38 ps for unloaded inverter ring oscillators and 185 ps for loaded NAND are demonstrated. A reduced operating voltage in the range of 2.2-2.5 V is chosen to optimize performance without compromising reliability. Shallow junctions with abrupt profiles are used to minimize device series resistance as well as gate-to-source/drain (S/D) overlap capacitance. Dural poly (n/sup +/ and p/sup +/) gates are used to avoid buried-channel operation pFETs, resulting in superior short-channel characteristics. Poly and S/D sheet resistances are lowered, using a thin salicide (TiSi/sub 2/) process. >

KRS-XE, a high performance chemically amplified photoresist designed specifically for e-beam mask making applications, has been enhanced to achieve reduced “footing” on chrome oxide surfaces while still maintaining the original lithographic characteristics that make KRS-XE a promising mask making candidate. These attributes include high resolution, superior bake latitudes, high vacuum stability, coated shelf life of greater than 2 months, and, most notably, the absence of a post exposure bake. In conjunction with the footing reduction the requisite sensitivity requirement of

Several contact hole shrinking techniques have been discussed in the literature recently. Two notable techniques; Resolution Enhancement Lithography Assisted by Chemical Shrink (RELACSTM) and Resist Flow Process (RFP) were investigated in conjunction with several commercially available high activation energy chemically amplified materials and one bilayer material. During the course of this study the unique set of advantages along with the inconveniences associated with each technique were explored. It was not only the lithographic attributes of each technique that were of interest, but also characteristics that would effect manufacturability. To that end, experiments were designed so that standard statistical techniques could be employed at the data analysis stage. The attributes of interest were the amount and control of shrinkage, nested and isolated feature bias, process window comparisons, and line edge roughness. It will be shown how several of theses attributes are directly related to manufacturing issues such as lot-to-lot repeatability and linewidth variations across the wafer.

As thin film imaging becomes an accepted means of producing high-resolution microelectronics features, a host of new challenges has emerged. A dose dependence on resist thickness has been observed and systematically measured for chemically amplified resists exposed with 75 keV electron beam radiation. The required dose to print 100nm images increased as the thickness of the film decreased. A physiochemical explanation for this dependence was sought which included exploring thickness-induced variations in thermal characteristics of the resist film. Over the range of film thickness examined, 80-360nm, these parameters were deemed unlikely contributors to this phenomenon. Ultimately the data suggests that the dose variation with thickness may correlate to differences in the population of chemically effective electron with energies in the range of 10 to 100 eV that are responsible for the sensitization of electron beam resists.

Patterning sub-150 nm features in dielectric stacks using single layer resist processes in conjunction with organic anti-reflective coatings (ARCs) is becoming very difficult. Typical organic ARC-open etch processes suffer from poor ARC-to-resist selectivities (~0.7), and are accompanied by critical dimension (CD) losses. The resist remaining is often not sufficient to prevent artifacts such as substrate microrevicing during subsequent etches. PECVD-Deposited titanium nitride and silicon oxynitride films have been investigated as ARC layers but their basic nature has caused residue formation at the resist/ARC interface. We have developed a PECVD-deposited material, TERA (Tunable Etch-Resistant ARC) that acts as an ARC at 248 nm and 193 nm wavelengths and provides excellent etch selectivity to resist surpassing those attained with organic ARCs. In addition, this material demonstrates excellent hard mask properties for subsequent dielectric etch steps. The optical properties of these films can be easily tuned to minimize substrate reflectance at either imaging wavelength by controlling the precursor composition and deposition conditions. The films are compatible with 248 nm and 193 nm resists - no footing, undercut or residue is observed during patterning. The films can be etched selectively to resist (selectivity ~2.5) that translates to less resist consumption during th ARC-open etch. Compared to resists, TERA demonstrates better etch resistance while patterning dielectric stacks - the silicon oxide-to-TERA Selectivity exceeds 8. In this paper, the excellent optical tunability and substrate reflectivity control achieved with TERA are discussed. Clean lithography using 248 nm, 193 nm and e- beam resists is shown. The etch characteristics of TERA in fluorocarbon and halogen-based plasma chemistries are discussed. Finally, the formation of 135 nm and 120 nm deep trench patterns in thick dielectric stacks using TERA in conjunction with commercial 248 nm and 193 nm resists, respectively is demonstrated. The extendability of this approach to pattern silicon without roughening or microrevicing using sub-200 nm thick resists is motivated.

The five major requirements for electron beam resists for chrome mask fabrication include high resolution, high speed, RIE etch resistance, thermal bake insensitivity, and long coated plate shelf life. High speed, high resolution and good RIE resistance are common attributes of chemically amplified resists (CAR) used primarily for Deep UV lithography. However, the environmental susceptibility to airborne amines, need for a long coated plate shelf life and the requirement for 140 Celsius postexpose bake (PEB) of some CAR or fundamental challenges of these families of resist for practical Cr lithography. We have been developing a series of fast amplified e beam resists which exhibit do not require PEB bake and are tolerant of airborne contaminants. The shelf life attributes of both negative and positive chemically amplified resists was examined and found to be susceptible to absorption of moisture. Some of the acid generators hydrolyzed in the dried films and led to changes in resist sensitivity or dark film loss. Long term film stability of CAR coated plates can be promoted by using hydrophobic solvents, stable acid generators, and most effectively by storage under anhydrous conditions.

A negative-tone bilayer thin film imaged (TFI) resist has been developed for extension of 248 nm optical lithography to sub-150 nm regime. The bilayer TFI resist system consists of a thin (0.2 um) silicon containing top imaging layer and a thick (0.7 - 0.8 um) highly absorbing organic underlayer. The chemically amplified negative-tone top layer resist comprises of three major components: an aqueous base soluble silicon containing polymer, poly(hydroxybenzylsilsesquioxane); a crosslinking agent; and a photoacid generator. The highly absorptive underlayer is a hard baked novolak resist or a DUV ARC. Imaging of the top layer resist has shown resolutions down to 137.5 nm for line/space features and 130 nm for isolated features with 248 nm exposure tools and chrome on glass masks. The O2 reactive ion etch (RIE) selectively of the top layers versus a novolak underlayer is more than 25:1 as a result of the high silicon content in the silicon containing polymer. Furthermore, residue-free and nearly vertical wall profile image transfer to the underlayer has been achieved with RIE. Application of the negative-tone bilayer resist to 150 nm Gbit DRAM critical level lithography has been demonstrated. Resist line edge roughness is also discussed.

Thin film interference plays an important role in critical dimension control of single layer resists causing large changes in the effective exposure dose due to small changes in optical phase. To overcome these problems bilayer resists have been proposed. Advantages to such systems include enhanced process latitude, enhanced resolution, and improved critical dimension control due to minimization of substrate reflectivity. In this paper, we have investigated the effects of the underlayer with respect to the optical properties as well as the chemical composition on the performance of bilayer resists for 248 nm lithography. The optimum optical constants (index of refraction n((lambda) ) and extinction coefficient k((lambda) )) of the underlayer were deduced by simulations. It was also found that with some underlayers, the optical properties could be tuned by controlling the processing conditions. Novolaks have been found to interact with the resist resulting in significant residue limiting the resolution of the 248 nm bilayer resist to 150 nm. Properly designing the underlayer with suitable optical constants and preventing resist/underlayer interaction resulted in 125 nm resolution with a 248 nm bilayer resist. We also investigated the use of an amorphous diamond-like carbon film as an underlayer material. Thin films, deposited by plasma enhanced chemical vapor deposition, offers advantages over spin on hard baked polymers because it can be deposited conformally with high optical purity. Furthermore, the composition and optical properties can be fine-tuned by changing the process parameters.

Non-chemically amplified resists offer advantages over chemically-amplified (CA) resists because they are less susceptible to temperature variations and contaminants. In order for non-CA resists to be viable, they have to perform lithographically at an equivalent level with the CA resists from the point of view of quantum yield, resolution and etch resistance. We report here on new non-CA resists based on polymer esters that undergo deesterification to the corresponding acids upon exposure to UV, x-ray and e-beam radiation. The efficiency of the radiation reaction is surprisingly high. The resulting poly acids are base soluble and can be employed as positive working resists. The resists are composed of polymers and copolymers of methacrylate esters. The sensitivity of one derivative to x-ray is 75 mJ/cm 2 and to e-beam is 1.0 (mu) C/cm 2 at 10 KV. Best resolution obtained was 125 nm with x-ray radiation.

Accurate stepper setup is essential for getting good overlay performance on product wafers. As part of a typical stepper setup procedure, one or more wafers are exposed, developed, aligned to the initial exposure, and then exposed again in order to determine the x/y baseline position and grid rotation. By removing the wafer from the chuck for processing (baking and development) before the alignment and exposure, both pre-aligner and stage errors are introduced. If the alignment and second exposure could be made without removing the wafer from the stepper chuck, these two sources of error could be eliminated. This is possible if the resist has a strong and immediate latent image after exposure.

Excimer laser lithography combined with chemically amplified resists offers a viable approach to lithography at 0.5 micrometers and below. APEX-E, a positive tone deep-uv resist used in conjunction with a 0.44 NA excimer laser stepper is capable of 0.35 micrometers resolution. To improve the process window for this resist while reducing the performance variability, the Taguchi method of quality control was employed. The baseline process for APEX-E was characterized, then subsequently used as a comparison to the optimized process as suggested by the Taguchi experiments.

For the patterning of sub-100 nm features, a clear understanding of the origin and control of line edge roughness (LER) is extremely desirable, from a fundamental as well as a manufacturing perspective. With the migration to thin photoresists coupled with bottom antireflective coating (ARC)-hardmask underlayers, LER analysis of the developed resist structures is perhaps an inaccurate representation of the substrate roughness after the etch process, since those underlayers can play a significant role in increasing/decreasing linewidth variations during the image transfer process and hence can impact the device performance. In this article, atomic force microscopy is used to investigate the contribution of the imaging resist sidewall topography to the sidewall roughness of the final etched feature in thin photoresists, ARC, and hardmasks. Resist systems suitable for 248 and 193 nm lithography as well as fluorine-containing resists were processed using N2-H2 or fluorocarbon plasma etch. It is shown that the interaction of different etch chemistries with existing sidewall profiles can result in loss of the original morphological information and creation of new spatial frequency domains that act as physical templates for subsequent image transfer processes. Excessive roughness transfer into the hardmask layer due to insufficient resist thickness or inadequate etch resistance originates from striation propagation from the resist layer into the hardmask layer. In the case of fluorine-containing materials, a decreased etch resistance and reduced initial film thickness values give rise to critical underlayer roughening during plasma etch. Based on the results shown, it is predicted that advanced resist systems for 157 nm lithography and beyond will require the use of ARC layers with built-in hardmask properties in those particular cases in which patterning of deep trenches is needed, in order to maintain LER values within acceptable levels.

Protective top coats and top antireflective coatings (ARCs) are frequently used in conjunction with chemically amplified resists. Top coats provide resistance to airborne contamination, and are particularly important where charcoal filtration is not available in the processing area. They are also useful in environments where delay times between process steps are not precisely controlled. Conductive top coats can be used for e-beam applications to reduce charging and image placement errors. Top ARCs are used to reduce reflections at the resist/air interface, thereby lowering the amplitude of the swing curve. All of these materials are applied on top of the photoresist after the postapply bake. In this article we report that depending on the subsequent processing conditions, top coatings can significantly impact the lithographic performance of the photoresist. Alterations in development rate, optical proximity effects, resist profile, and postexposure bake latitude have been observed as a result of processing with an additional top film. The primary mechanism responsible for these changes is an alteration of the diffusion characteristics of the photo acid generator during the deprotection step.

A six-mask 1-µm CMOS process with many self-aligned features is described. It uses a thin p-type epitaxial layer on a p+substrate and a retrograde n-well. Self-aligned TiSi 2 is formed on n+and p+diffusions to reduce the sheet resistance and to make butted source contacts. It is shown that n+poly-gated p-channel devices can be properly designed with low threshold magnitudes and good turn-off characteristics. With a 5-V supply, the minimum gate delay of unloaded CMOS ring oscillators is 150 ps/stage. Furthermore, it is demonstrated that this CMOS technology is latchup free since the holding voltage for latchup is higher than 5 V.

A six-mask 1-/spl mu/m CMOS process with many self-aligned features is described. It uses a thin p-type epitaxial layer on a p/sup +/ substrate and a retrograde n-well. Self-aligned TiSi/sub 2/ is formed on n/sup +/ and p/sup +/ diffusions to reduce the sheet resistance and to make butted source contacts. It is shown that n/sup +/ poly-gated p-channel devices can be properly designed with low threshold magnitudes and good turn-off characteristics. With a 5-V supply, the minimum gate delay of unloaded CMOS ring oscillators is 150 ps/stage. Furthermore, it is dernonstrated that this CMOS technology is Iatchup free since the holding voltage for Iatchup is higher than 5 V.

A 1 µm n-well CMOS technology with high latchup immunity is designed, realized, and characterized. The main features of this technology are : 1 MeV ion-implanted retrograde n-well, buried contact, arsenic-phosphorous double diffused n+/n-junction, self-aligned TiSi 2 on gate and diffusions with nitride spacer, and thin p epi on p+substrate. This technology has been demonstrated via the successful fabrication of high-performance 64K CMOS SRAM chips. It is also observed that the silicide plays an important role in latchup prevention since it reduces the emitter efficiencies of parasitic bipolar devices.

High performance fully scaled 0.5 μm complementary metal–oxide semiconductors very large scale integrated (CMOS VLSI) circuits have been fabricated using synchrotron x‐ray lithography technology. X‐ray lithography is employed at all levels to attain a minimum feature size of 0.5 μm. The wafer exposures are done at the VUV storage ring from the National Synchrotron Light Source, Brookhaven National Laboratory. A stepper built at IBM Yorktown Heights is used at the beamline to perform the wafer exposures. All the lithography levels are aligned to the prefabricated 0.5 μm deep silicon trench zero level with an overlay less than 0.1 μm (1σ) between levels. Single level resists (both positive and negative) are used throughout the entire CMOS process. Linewidth control better than 0.01 μm and alignment tolerance less than 0.10 μm are accomplished. The patterning of this x‐ray lithography mask is accomplished through a vector scan electron beam direct writing system. Masks made of boron doped silicon membranes w...