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A K-band complementary metal-oxide-semiconductor (CMOS) differential cascode power amplifier is designed with the thin-oxide field effect transistor (FET) common source (CS) stage and thick-oxide FET common gate (CG) stage. Use of the thick-oxide CG stage affords the high supply voltage to 3.7 V and enables the high output power. Additionally, simple analysis shows that the gain degradation due to the low cut-off frequency of the thick-oxide CG FET can be compensated by the high output resistance of the thick-oxide FET if the inter-stage node is neutralized. The measured results of the proposed power amplifier demonstrate the saturated output power of the 23.3 dBm with the 31.3% peak power added efficiency (PAE) at 24 GHz frequency. The chip is fabricated in 65-nm low power (LP) CMOS technology and the chip size including all pads is 700 μm × 630 μm.

A band-offset-based unified-RAM (URAM) cell fabricated on a Si/Si1-yCy substrate is presented for the fusion of a nonvolatile memory (NVM) and a capacitorless 1T-DRAM. An oxide/nitride/oxide (O/N/O) gate dielectric and a floating-body are combined in a FinFET structure to perform URAM operation in a single transistor. The O/N/O layer is utilized as a charge trap layer for NVM, and the floating-body is used as an excess hole storage node for capacitorless 1T-DRAM. The introduction of a pseudomorphic SiC-based heteroepitaxial layer into the Si substrate provides band offset in a valence band. The FinFET fabricated on the energy-band-engineered Si1-yCy substrate allows hole accumulation in the channel for 1T-DRAM. The band-engineered URAM yields a cost-effective process that is compatible with a conventional body-tied FinFET SONOS. The fabricated URAM shows highly reliable NVM and high-speed 1T-DRAM operations in a single memory cell.

High-performance sub-60 nm Si/SiGe (Ge:~75%)/Si heterostructure quantum well pMOSFETs with a conventional MOSFET process flow, including gate-first high-kappa/metal gate stacks with ~1 nm equivalent oxide thickness, are demonstrated. For the first time, short gate length (L g) devices demonstrate not only controlled short channel effects, but also an excellent on-off current (I on/I off) ratio (~5times104 55-nm L g). The intrinsic gate delay of these heterostructures is ~3 ps at I on/I off~104. OFF-state leakage was minimized by controlling the defects in the epitaxial films. Finally, these short L g devices, when benchmarked against state-of-the-art Si channel pMOSFETs, appear to be very promising in replacing the Si channel in CMOS scaling.

We report a novel Si/Si1-xGex channel with improved current drivability and reliability using a buried Si0.99C0.01. It is also found that the Si/Si1-xGex/Si0.99C0.01 structure is effective in reducing Ge out-diffusion which helps to improve gate dielectric interface quality.

We report a novel Si/Si1-xGex channel with improved noise, current drivability, and reliability using a buried Si0.99C0.01 which can induce higher channel strain for the same Ge concentration. High-k dielectrics on Si/Si1-xGex. with buried Si0.99C0.01 show lower charge trapping, better leakage current distribution and less ftathand voltage shift. Si/Si1-xGex. channel p-MOSFET with the buried Si0.99C0.01 shows drive current improvement of up to 20% and better noise immunity.

The thermal stabilities of MOSFETs with high-K gate dielectric on both Si/ultrathin Ge/Si (SGS) and strained Si on relaxed Si1?xGex (SS) substrates are studied. Though an initial drivability enhancement of 29% is shown for the SGS nMOSFET, annealing at 750 ?C has resulted in drastic degradation in its drivability, lowering its Id beyond that of the Si nMOSFETs by 52%. Despite lowering in the junction leakage current, Ge diffusion to the near surface region, indicated by Vth and surface roughness change, degrades the SGS device performance significantly. For the SS nMOSFET, drivability varies with Ge content, whereby a maximum of 86% improvement over that of the Si nMOSFET is observed for 30% Ge. In contrast to the SGS nMOSFET, the SS nMOSFET is able to retain its Id improvement, even after annealing at 950 ?C, as the in-plane tensile strain is preserved. Ge diffusion to the surface does not affect the device significantly, as the strained Si thickness is about 10 nm compared to a Si cap thickness of only 1.5 nm for the SGS substrate.

We propose a novel approach to engineering floating gates (FGs) of flash memory cells, namely, carbon incorporation into polysilicon FGs. This technique demonstrated an improvement in retention and a larger program/erase Vt window, particularly for smaller capacitance coupling ratio cells, which is important for future scaled flash memory cells.

A novel fusion memory is proposed as a new paradigm of silicon based memory technology. An O/N/O gate dielectric and a floating body are combined with a FinFET, and the non-volatile memory (NVM) and high speed capacitorless 1T-DRAM are performed in a single transistor. A nitride trap layer is used as an electron storage node for NVM, and hetero-epitaxially grown Si/Si1-xGex energy band engineered bulk substrates allow excess hole storage for 1T-DRAM. Highly reliable 1T-DRAM and NVM are demonstrated.

A FinFET-based unified-RAM (URAM) using the band offset of Si/SiC is demonstrated for the fusion of a non-volatile memory (NVM) and capacitorless 1T-DRAM operation. An oxide/nitride/oxide (O/N/O) gate dielectric and a floating body caused by the band offset are combined in a bulk FinFET to allow two memory operations in a single transistor. The device is fabricated on an epitaxially grown Si/SiC substrate and its process is fully compatible with a conventional bulk FinFET SONOS. Highly reliable NVM and high speed 1T-DRAM operation are confirmed in a single URAM cell.

A GaAs defect-free epitaxial layer has been grown on Si via a Ge concentration graded SiGe on insulator (SGOI) for application in high channel-mobility metal-oxide-semiconductor field effect transistor. The SGOI layer, 42nm thick, serves as the compliant and intermediate buffer to reduce the lattice and thermal expansion mismatches between Si and GaAs. A modified two-step Ge condensation technique achieves the surface Ge concentration in SGOI as high as 71%. It is also found that low-temperature migration enhanced epitaxy during the initial GaAs nucleation on the SGOI surface is critical to obtain a device quality GaAs layer by epitaxial growth.

A novel fabrication technique to grow device quality GaAs on Si substrate is proposed using thin graded SiGe-on-insulator (SGOI) substrate. Combination of low-temperature GaAs molecular beam epitaxy (MBE) growth technique, low-temperature GaAs migration enhanced epitaxy (MEE) technique, and modified two-step Ge condensation technique has demonstrated successful growth of 10-nm GaAs layer grown on a tensile strained 42-nm graded SGOI layer.