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Although, today, the main method for pattering almost all integrated circuits (ICs) is photolithography, charged-particle lithography – where charged particles (electrons, ions) are used for patterning – already has a wide range of applications. Electron beam lithography (EBL) is currently utilized for fabricating the photomasks essential for photolithography, as a time- and cost-effective technique for early device and technology development, and also for fabricating the imprint templates necessary for the emerging technique of nanoimprint lithography (NIL). All of these applications are enabled by single-beam writing techniques, which are undergoing continuous improvement. However, as photomask costs have increased, and continue to increase, it has become almost untenable to produce high-end ICs in low volume. Hence, today the use of field-programmable gate arrays (FPGAs) has surpassed that of the faster and more highly integrated application-specific integrated circuits (ASICs). Consequently, promising new multiple-beam writing techniques are currently under development, known as maskless lithography (ML2), for the volume production of ICs. Ion beam lithography (IBL) represents an alternative approach for the fabrication of imprint templates for NIL, with the advantage of not requiring resist processing. Currently, both EBL and IBL are the only viable methods for fabricating nano-electromechanical systems and nanotechnology devices, and therefore are essential tools for the emerging nanotechnology. Keywords: electron beam lithography; chemically amplified resist (CAR); photomask fabrication; direct-write; maskless lithography (ML2); nanoimprint template fabrication; ion beam lithography; direct-structuring

Progress towards 65 nm next-generation lithography requires unprecedented global CD uniformity, with the actual ITRS 2002 roadmap proposing 4.2 nm 3/spl sigma/ (dense lines) for 65 nm binary masks. Since resolution requirements are satisfied only by using chemically amplified resists (CARs), exposure and post-exposure bake (PEB) are key processes to successful mask making, both introducing global CD errors. Develop and etch processes potentially contribute further global CD errors. The global CD uniformity can be improved significantly by adaptive PEB, especially for CARs showing moderate to strong PEB sensitivity, like NEB22. With the 25-zone hotplate of the APB5500 bake system, facilitated through a novel calibration mask with 25 equidistant temperature sensors within the resist plane, an appropriate temperature profile can be applied during PEB. This temperature profile is automatically calculated by an adaptive optimization algorithm, based on 2-dimensional spline fitting of a CD measurement. A CD-uniformity improvement (dense lines) from 4.8 nm 3/spl sigma/ to 3.9 nm 3/spl sigma/ (/spl cong/20%) on a state-of-the-art production mask is achieved for the chrome layer (ASI, after strip inspection).

Negative-tone chemically amplified resists (nCARs), like NEB22 are promising candidates for next-generation lithography, e.g. 90 nm and 65 nm technology node and next-generation lithography. For these resists, e-beam exposure and post-exposure bake (PEB) are most critical processes, since these resists show a strong sensitivity to post-exposure delay (PED) in vacuum during e-beam writing of about 0.5 nm/h, and in air while waiting for PEB. Further, such resists show a strong PEB temperature sensitivity of up to 8 nm/K. The multi-zone hotplate approach of the APB AFB 5500 bake system with its use prior temperature uniformity results in excellent global CD-uniformity already. However, all kinds of systematic large area effects of processes, e.g. blank coat/bake, exposure, PED, the PEB itself, etch loading, etc. may transfer in additional systematic CD-errors. Such systematic, repeatable errors can be reduced during PEB by superimposing an appropriate non-uniform temperature profile onto the regular, optimized uniform bake temperature profile, thereby compensating for such CD-non-uniformities. The required temperature profile can automatically be calculated from a suitable gobal CD measurement, determined in a typical process flow. The compensation of CD-errors resulting from vacuum PED and hotplate temperature characteristics is demonstrated here, by using automated temperature profile calculation. The global CD uniformity was improved significantly, the achieved results show a typical reduction of about 20-30%, from a total global range of about 9nm to about 6-7nm on leading-edge production photomasks.