Search

Low temperature (≤400 °C) formation of orientation-controlled large (≥10 µm) Ge-on-insulator (GOI) structures is desired to fabricate 3-dimensional large-scale integrated circuits (LSIs), where Ge-based functional devices are stacked on Si-LSIs. For this purpose, Si-seeded pulse-laser annealing (PLA) combined with low-temperature substrate heating (≤400 °C) has been developed. Here, a-Ge stripes on Si substrates partially covered with insulating films are subjected to PLA, where single edges of the a-Ge stripes directly contact Si-seeding substrates through opening windows of insulating films. PLA at room temperature generates lateral growth of Ge layers from Si-seeding substrates. However, the growth length is short (~1 µm), which is attributed to very short melting time. To increase the melting time, low-temperature (≤400 °C) substrate heating during PLA is examined. As a result, very large (~20 µm) orientation-controlled GOI is obtained by combining substrate heating (400 °C) with PLA. Detailed electron microscopy analysis reveals very high crystallinity of the grown layers. Consequently, high-quality rapid-melting growth of Ge becomes possible at a low processing temperature of ~400 °C. This thermally-assisted (~400 °C) Si-seeded PLA will facilitate realization of 3-dimensional LSIs.

Structural and electrical properties of a Ge(111) layer directly grown on a Si(111) substrate are studied. Via optimized two-step growth manner, we form a high-quality relaxed Ge layer, where strain-relieving dislocations are confined close to a Ge/Si interface. Consequently, a density of holes, which unintentionally come from crystal defects, is highly suppressed below 4 × 10 16 cm − 3 , which leads to significantly high hole Hall mobility exceeding 1500 cm 2 /Vs at room temperature. By layer transfer of the grown Ge layer, we also fabricate a Ge(111)-on-Insulator, which is a promising template for high-performance Ge-based electronic and photonic devices.

GeSn with a high substitutional Sn concentration (> 7%) is an attractive direct band gap material for high-efficiency photodevices that can be merged with large-scale integrated circuits (LSIs). To achieve GeSn with high Sn concentration, low-temperature solid-phase epitaxy using amorphous-GeSn (a-GeSn) (Sn concentration: 10%–36%)/crystal-Ge (c-Ge) stacked structures was investigated. Solid-phase growth of GeSn was enhanced as Sn concentration was increased, which enabled epitaxial growth at very low temperature (150–200 °C). Interestingly, concentrations of substitutional Sn increased with decreasing growth temperature. As a result, epitaxial growth of GeSn with substitutional Sn concentrations of ~ 8% was achieved by decreasing the growth temperature to 150 °C using a-GeSn (Sn concentration: 36%)/c-Ge stacked structures. This technique is expected to be useful to realize multi-function LSIs, where high-efficiency photodevices are integrated with transistors.

I NTRODUCTION Low-temperature (≤300oC) formation of quasi-single crystal SiGe, i.e., orientation-controlled large-grain crystal (≥10 μm) SiGe, on insulator is desired for realization of advanced flexible electronics, where high-speed transistors and high-efficiency optical devices are integrated on flexible plastics substrates (softening temperature: ~350°C). This is because SiGe provides higher carrier mobility and superior optical properties compared with Si. Recently, we developed gold-induced layer-exchange crystallization (GIC) using a-Ge/Au stacked structures.[1-3] This enabled selective formation of (100)- or (111)-oriented large-grain Ge (≥20 μm) through controlling nucleation during GIC by using anisotropic surface energy on substrates.[1] We have developed this technique onto plastic and realized orientation-controlled large-grain crystals on flexible plastic substrates with low concentration holes (~2×1017 cm-3), which enables high carrier mobility (~160 cm2/Vs).[2,3] However, reports of orientation-controlled growth by GIC are limited to pure Ge crystals so far. In the present study the GIC technique is developed to SiGe. Consequently, quasi-single crystal SiGe is achieved on insulating substrates at low temperatures (~300oC). EXPERIMENTAL The sample structure and experimental procedure are schematically shown in Fig. 1. In the experiment, fused-quartz chips were employed as substrates. On the substrates, a-SiGe (Ge concentration: 0-100%, thickness: 100 nm) /Au (thickness: 100 nm) stacked structures were formed. Here, amorphous Al2O3 interface-layers (thickness: 4-7 nm) were introduced between a-SiGe and Au layers as diffusion barrier to make interface-nucleation dominate over random bulk-nucleation in Au layers.[1] These samples were annealed at 250-300oC to induce crystallization. The grown layers were analyzed by Nomarski optical microscopy, electron backscattering diffraction (EBSD), and micro-probe Raman scattering spectroscopy (excitation-laser spot-diameter: ~1 μm). The Nomarski optical microscopy observations were carried out from the back sides of the samples through the transparent quartz substrates to characterize the bottom layers. RESULTS AND DISCUSSION The growth features of samples with various Ge fractions and Al2O3 interface layer thicknesses were investigated by Nomarski optical microscopy observations after annealing at 250°C for 50 h. Typical Nomarski micrographs of samples with Ge concentrations of 50% and 100% are shown in Figs. 2(a)-2(b) and 2(c)-2(d), respectively. In these micrographs, dark and bright contrast regions are observed. Micro-probe Raman measurements revealed that the dark regions dominantly observed in Figs. 2(a), 2(c), and 2(d) are crystal, while bright regions dominant in Fig. 2(b) are not crystal. These results indicate that layer exchange crystallization occurs for the samples shown in Figs. 2(a), 2(c), and 2(d), while it does not proceed for the sample shown in Fig. 2(b). EBSD measurements revealed that the grown layers for Fig. 2(d) consisted of (111)-oriented large-grains (≥10 μm). On the other hand, grown layers for Figs. 2(a) and 2(c) consisted of randomly-oriented small-grains (1-3 μm). Here, we examined the Nomarski micrographs of a no-grown Si0.5Ge0.5 sample (diffusion barrier thickness: 5 nm), shown in Fig. 2(b). It is found that nuclei are formed for the Si0.5Ge0.5 sample, though lateral growth does not proceed from the nuclei. From this finding, it is speculated that for the Si0.5Ge0.5 sample (diffusion barrier thickness: 5 nm), (111)-oriented nucleation occurs at Au/SiO2 interface. However, lateral growth does not proceed even after long time annealing. Thus, layer-exchange is not observed. It is suggested that lateral crystallization in GIC is retarded by Si introduction. This consideration triggers an idea that (111)-oriented large-grains can be obtained even for the Si0.5Ge0.5 sample by generating lateral growth from nuclei. Thus, we examine annealing at a higher temperature of 300°C. A Nomarski micrograph of Si0.5Ge0.5 sample (diffusion barrier thickness: 5 nm) after annealing at 300°C for 50 h is shown in Fig. 3(a). Micro-probe Raman measurements reveled layer-exchange crystallization in the entire area. The crystal structures of the grown layer are examined by EBSD measurements. The result is shown in Fig. 3(b), which reveals (111)-oriented large-grains (≥10 μm). As a result, quasi-single crystal SiGe is realized on insulator. This technique will facilitate realization of advanced flexible electronics. ACKNOWLEDGEMENT Part of this work was supported by JSPS Core-to-Core Program, A. Advanced Research Networks. References [1] J.-H. Park et al., Appl. Phys. Lett. 103, 082102 (2013). [2] J.-H. Park et al., Jpn. J. Appl. Phys. 53, 020302 (2014). [3] J.-H. Park et al., Appl. Phys. Lett. 104, 252110 (2014). Figure 1

Introduction Formation of crystalline GeSn film on insulator with high Sn concentration exceeding thermal equilibrium solid-solubility is strongly expected to realize high-speed thin film transistors. To explore non-thermal equilibrium processing [1], we examined crystallization of amorphous-GeSn (a-GeSn) with various modulated Sn concentration by pulsed laser annealing (PLA). In the present study, we focus on the influence of the Sn concentration on crystallization of a-GeSn by PLA. Experimental Procedure Schematic sample structure and PLA conditions are shown in Fig.1. A-Ge1-xSnx (0≦x≦0.2) films (thickness: 100 nm) were deposited on quartz substrates by a molecular beam technique. These samples were irradiated with a pulsed laser (energy : 10 - 230 mJ/cm2, pulse period : 1 sec, pulse number : 100 shot). The laser annealed regions were analyzed by Nomarski microscopy and Raman scattering spectroscopy. Results and Discussion Nomarski micrograph and Raman spectra of Ge0.8Sn0.2 samples before and after PLA with various energy are summarized in Fig. 2. In the samples after PLA, the contrast-changed regions were observed, compared with the as-deposited sample. Here, the contrast becomes stronger with increasing energy from 50 mJ/cm2 to 170 mJ/cm2, and finally the GeSn layer was damaged for energy of 230 mJ/cm2. Raman spectra reveales that Ge0.8Sn0.2 is crystallized on insulating substrates by 50 - 170 mJ/cm2 PLA. The process-window to achieve crystalline GeSn is summarized in Fig. 3(a), where the energy for starting crystallization and the energy just before damaging are indicated as Ecryst. and Edamage , respectively. Substitutional Sn concentration estimated from shift of Ge-Ge peak obtained by Raman measurements is shown in Fig. 3(b). The process window necessary for crystallization is significantly expanded by introducing Sn, i.e. 16 mJ/cm2 for Ge, ~ 130 mJ/cm2 for GeSn. High Sn concentration exceeding thermal equilibrium solid-solubility is obtained by PLA, for all GeSn samples. Interestingly, for samples with initial Sn concentration of 5 % and 10 %, almost all Sn atoms are incorporated into substitutional site, while for 20 % sample, only half of Sn atoms are incorporated into substitutional site. The detailed physics will be discussed in the presentation. References [1] M. Kurosawa, et al., Appl. Phys. Lett. 104, 061901 (2014). Figure 1

Low-temperature (≤200°C) formation of GeSn (substitutional Sn concentration: >8%) films on insulator is desired to realize high-speed thin film transistors (TFTs) and high-efficiency optical devices on flexible plastic substrates (softening temperature: ∼200°C). This is because GeSn (substitutional Sn concentration: >8%) has higher carrier mobility than Si and Ge due to the direct-transition energy band structure with smaller effective mass of carriers.

High-quality Ge-on-insulator (GOI) structures are essential to realize next-generation large-scale integrated circuits, where GOI is employed as active layers of functional devices, as well as buffer layers for epitaxial growth of functional materials. In line with this, in-depth analysis of crystallinity of rapid-melting-grown GOI is performed. Structural and electrical measurements combined with a thinning technique reveal that the crystallinity of GOI (500 nm thickness) is very high and uniform in-depth direction, where high hole mobility (~ 1000 cm 2 /V s) is achieved throughout the grown layers. These findings open up a possibility of application of rapid-melting-grown GOI to various advanced functional devices.

We demonstrate the (111)-oriented Ge-on-Insulator (GOI) formed by Ge epitaxial growth on a Si(111) and the layer transfer technique. The two-step growth manner, involving low-temperature growth of a thin Ge layer and subsequent high-temperature growth of a thick Ge layer, enables us to obtain high-quality tensile-strained epitaxial Ge(111) on Si(111). It is found that the strain amount straongly depends on the growth temperatures and we find an optimal growth temperature. We also developed a chemical mechanical polishing (CMP) method modified for Ge, offering the ultra-smooth Ge(111) surface. The polished epitaxial Ge is bonded on a SiO2/Si, followed by the selective etching of Si and the final CMP of Ge. As a result, we achieve the high-quality 200-nm-thick tensile-strained Ge(111)-OI with an ultra-smooth surface, on which, furthermore, we demonstrate the growth of an epitaxial metallic silicide for the metal source/drain in spintronic devices as well as advanced Ge channel devices.

We have explored an effect of the interface resistance of Fe3Si/n+-Ge Schottky-tunnel contacts on spin accumulation created electrically in n-Ge. Using the Schottky-tunnel contacts with a relatively high interface resistance, we can clearly detect spin-accumulation signals in n-Ge even at room temperature, meaning that the use of highly resistive Schottky tunnel contacts is effective to electrically create large spin accumulation. Since such highly resistive source and drain electrodes are not available for next-generation Ge-based spintronic applications with ultra-low power consumption, the development of highly spin-polarized spin injectors such as half-metallic materials is essential from now on.

For high-performance spin injectors in silicon (Si)-based spintronic applications, we have explored the growth technique of quaternary Co-based Heusler-compound Co2FeSi0.5Al0.5 on Si(111) by using low-temperature molecular beam epitaxy (LTMBE). In our previous study, Al co-deposition induced an interfacial reaction between Co2FeSi1 − xAlx and Si. Here, we dramatically improve the Co2FeSi0.5Al0.5/Si heterostructures by introducing a nonstoichiometric LTMBE technique. Atomically smooth Co2FeSi0.5Al0.5/Si heterointerfaces and L21-ordered Co2FeSi0.5Al0.5 films are simultaneously achieved. Even in as-grown conditions, the magnetic properties of the Co2FeSi0.5Al0.5 layers are nearly equivalent to those of the heat-treated ones reported on MgO. This study gives important knowledge to realize the optimized highly spin-polarized ferromagnet/Si heterointerfaces for next-generation Si-based spintronic devices.

High-speed fully depleted thin-film transistors (TFTs) for low-power consumption are required for next-generation electronics, such as three-dimensional large-scale integrated circuits and advanced system-in-displays. For this purpose, high-carrier-mobility semiconductor thin-films (thickness: ≤∼50 nm) on insulator structures should be fabricated under low-temperature processing conditions (≤500 °C). To achieve this, solid-phase crystallization of amorphous GeSn (a-GeSn) with low Sn concentration (2%) is investigated for a wide range of film thicknesses (30 − 200 nm), where thin a-Si underlayers (thickness: 0 − 20 nm) are introduced between a-GeSn films and substrates. GeSn is polycrystallized by annealing at 450 °C, keeping Si underlayers amorphous. Crystal grains of almost identical sizes are obtained for GeSn thicknesses of 30 − 50 nm, though grain sizes significantly decrease for thicknesses exceeding 50 nm owing to enhanced bulk nucleation. A detailed analysis of GeSn films (thickness: 50 nm) reveals that grain sizes are decreased by introducing a-Si underlayers (thickness: 3 − 20 nm), e.g., from ∼10 μm to 2 − 3 μm. This phenomenon is attributed to the change in dominant nucleation sites from the interface to the bulk, which significantly decreases grain-boundary scattering of carriers through a decrease in the barrier heights at grain boundaries. As a result, a high carrier mobility of 200 − 300 cm2/V s is realized for GeSn thin-films (thickness: 30 − 50 nm) grown with a-Si underlayers. The mobility (200 − 300 cm2/V s) is the largest ever reported data for Ge and GeSn thin-films (thickness: 30 − 50 nm) grown at low temperatures (≤500 °C). This technique will facilitate the realization of high-speed fully depleted TFTs for next-generation electronics.

To develop a new low-temperature crystallization technique, annealing characteristics of a-GeSn/Si (100) structures are investigated. It is revealed that epitaxial growth accompanying Si-Ge mixing is generated at temperatures in the liquid-solid coexisting region of the Ge-Sn system. The annealing temperature necessary for epitaxial growth is significantly decreased by increasing annealing time and/or Sn concentration. Consequently, epitaxial growth at 300°C becomes possible. These findings are expected to be useful to realize next-generation large-scale integrated circuits, where various multi-functional devices are integrated.

INTRODUCTION To break through the scaling limit of Si-LSIs, development of functional materials becomes essential. GeSn is a big candidate for this purpose, because GeSn provides direct energy-band gap and very light carrier effective-mass [1,2]. In line with this, development of a formation technique of high-quality GeSn is desired. Our approach for formation of high-quality GeSn is utilization of liquid-phase reaction. To induce liquid-phase crystallization at low temperatures, we propose to employ a-Ge/Sn stacked structures deposited on c-Ge as a starting material. To examine this idea, in the present study, we investigate growth characteristics of a-Ge/Sn/c-Ge stacked structures.

Research and development for new semiconductor devices which enable ultrahigh speed operation, ultralow power dissipation, and/or multi-functional operation are strongly required to overcome a scaling limit of the complementary metal-oxide-semiconductor (CMOS) performance. Thus, Si-based heterostructure technologies have been widely developed over the last quarter century [1]. The hetero-epitaxial growth of III-V semiconductors and ferromagnetic Heusler alloys is the typical example, which achieves optical emission and spin injection on Si and Ge substrates [2-6]. In order to create multi-functional large scale integrated circuits (LSI), such new materials should be stacked on the group-IV semiconductor platform with high carrier mobilities. Consequently, development of high quality Ge-on-insulator (GOI) structures becomes essential. In line with this, we have been developing SiGe mixing triggered rapid-melting growth [7-8]. This achieves defect-free Ge and SiGe single crystals on insulating substrates. In addition, hybrid-formation of (100), (110), and (111) GOI is achieved on (100) Si platform by using metal-induced crystallization methods for Si micro-seed formation. Here, we emphasize that such hybrid-structures are so-called artificial crystals, because no single-crystalline substrates have been used to initiate Ge rapid-melting growth. The present paper reviews our recent progress in this novel growth technique [7-18]. Main subjects to be discussed in this symposium are as follows

INTRODUCTION SiGe-on-insulator and Ge-on-insulator structures are essential to realization of advanced LSIs. Recently, we developed SiGe mixing triggered liquid-phase epitaxy (LPE) of a-Ge [1,2], which achieved high quality giant Ge single crystals (length: ~1cm) on insulating substrates [3]. In course of the study, we encountered a phenomenon that large grain Ge single crystals (~5 m) grew on insulating substrates without any seed [2]. On the other hand, SiGe has solidification-completing temperatures significantly different from solidification-initiating temperatures in melting growth. Thus, longer growth times are expected for SiGe compared with pure Ge. This triggered an idea that much larger crystal grains should be obtained, if a-SiGe films were melt-grown instead of a-Ge. To examine this idea, we investigate rapid-melting growth of a-SiGe on insulating substrates without any seed.

For spintronic applications compatible with silicon (Si) large scale integrated circuits, we have so far developed the growth technique of a Co-based Heusler-compound film, Co2FeSi, on Si by using low-temperature molecular beam epitaxy. In this study, we explore an addition technique of a fourth element, Al, to the Co2FeSi films in order to tune the number of the valence electrons and to realize the high-performance spintronic devices. We can demonstrate L21-ordered Co 2 F e S i 0.5 A l 0.5 films using Al co-deposition although 4-nm-thick reaction layers are formed at the interface. A possible mechanism of the epitaxial growth of quaternary Co 2 F e S i 1 − x A l x films on Si is discussed.

Liquid-phase epitaxial growth of Ge islands on insulator (GOI) using Ni-imprint-induced Si (1 1 1) micro-crystal seeds (∼1 μmϕ) is proposed. As a result, single-crystalline GOI (1 1 1) structures with large area (∼10 μmϕ) are realized. The transmission electron microscopy observations reveal no dislocation or stacking fault in the laterally grown regions. Moreover, the Raman measurements show that the tensile strain (∼0.2%) which enhances the carrier mobility is induced in the growth regions. This new method can be employed to realize the multi-functional SiGe large scale integrated circuits.

We have investigated the Si-seeding rapid-melting process and demonstrated the formation of giant Ge stripes with (100), (110), and (111) orientations on Si (100), (110), and (111) substrates, respectively, covered with SiO2films. We revealed that crystallization is triggered by Si-Ge mixing in the seeding regions in this process. Based on this mechanism, we have proposed a novel technique to realize orientation-controlled Ge layers on transparent insulating substrates by using Si artificial micro-seeds with (100) and (111)-orientations. This achieved epitaxial growth of single crystalline (100) and (111)-oriented Ge stripes on quartz substrates. The Ge layers showed a high hole mobility exceeding 1100 cm2/Vs owing to the high crystallinity.

High-quality orientation-controlled Ge on insulator (GOI) structures are essential to realize high-performance thin-film transistors (TFTs) and epitaxial templates for multifunctional 3-dimensional large-scale integrated circuits (3D-LSIs). We have investigated the Si-seeding rapid-melting process and demonstrated formation of giant Ge stripes with (100), (110), and (111) orientations on Si (100), (110), and (111) substrates, respectively, covered with SiO2 films. We revealed that crystallization is triggered by Si-Ge mixing in the seeding regions in this process. Based on this mechanism, we have proposed a novel technique to realize orientation-controlled Ge layers on transparent insulating substrates by using Si artificial micro-seeds with (100) and (111)-orientations. This achieved epitaxial growth of single crystalline (100) and (111)-oriented Ge stripes on quartz substrates. The transmission electron microscopy observations revealed no-defects in the laterally grown Ge regions. The Ge layers showed a high hole mobility exceeding 1100 cm2/Vs owing to the high crystallinity. This novel SiGe mixing-triggered growth technique opens up the possibility of the next-generation TFTs and multifunctional 3D-LSIs.

High-speed thin-film transistors (TFTs) are required to develop the next generation of electronics, such as three-dimensional large-scale integrated circuits and advanced system-in-displays. For this purpose, high-carrier-mobility semiconductor films on insulator structures should be fabricated with low-temperature processing conditions (≤500 °C). To achieve this, we investigate solid-phase crystallization of amorphous-GeSn (a-GeSn) films (Sn concentration: 2% and thickness: 50–200 nm) on insulating substrates, where thin a-Si under-layers (thickness: 0–20 nm) are introduced between a-GeSn films and insulating substrates. The GeSn films are polycrystallized by annealing (450 °C, 20 h) for all samples irrespective of a-GeSn and a-Si thickness conditions, while the Si films remain amorphous. Analysis of crystal structures of GeSn films (thickness: 50 nm) reveals that grain sizes decrease from ∼10 μm to 2–3 μm by the introduction of a-Si under-layers (thickness: 3–20 nm). This phenomenon is attributed to the change in dominant nucleation sites from the interface to the bulk, which significantly decreases grain-boundary scattering of carriers through a decrease in the barrier heights at grain boundaries. Bulk-nucleation further becomes dominant by increasing the GeSn film thickness. As a result, a high carrier mobility of ∼550 cm2/V s is realized for GeSn films (thickness: 100 nm) grown with a-Si under-layers. This mobility is the largest among ever reported data for Ge and GeSn grown on an insulator. This technique will facilitate realization of high-speed TFTs for use in the next generation of electronics.At the request of the authors, this article is being retracted effective 11 July 2018.High-speed thin-film transistors (TFTs) are required to develop the next generation of electronics, such as three-dimensional large-scale integrated circuits and advanced system-in-displays. For this purpose, high-carrier-mobility semiconductor films on insulator structures should be fabricated with low-temperature processing conditions (≤500 °C). To achieve this, we investigate solid-phase crystallization of amorphous-GeSn (a-GeSn) films (Sn concentration: 2% and thickness: 50–200 nm) on insulating substrates, where thin a-Si under-layers (thickness: 0–20 nm) are introduced between a-GeSn films and insulating substrates. The GeSn films are polycrystallized by annealing (450 °C, 20 h) for all samples irrespective of a-GeSn and a-Si thickness conditions, while the Si films remain amorphous. Analysis of crystal structures of GeSn films (thickness: 50 nm) reveals that grain sizes decrease from ∼10 μm to 2–3 μm by the introduction of a-Si under-layers (thickness: 3–20 nm). This phenomenon is attributed to the...

We investigated the epitaxial growth of high-quality Fe3Si thin films on Si(111) and demonstrated electrical injection and detection of spin-polarized electrons in Si through the Fe3Si/Si Schottky-tunnel contacts. TEM observations and analyses of electron diffraction patterns revealed that precisely controlling the Fe/Si ratio during growth is important to obtain well ordered Fe3Si structures and atomically abrupt heterointerfaces at the same time. The electrical properties of Fe3Si/Si Schottky diodes with various carrier concentrations were also examined, and highly transparent tunnel contacts were demonstrated. We were able to clearly detect nonlocal spin signals in Si at 150K using Fe3Si/Si lateral four-probe devices.

The electrical characteristics of epitaxially grown Fe3Si/Si structures were investigated. From the I-V and C-V measurements, excellent Schottky barrier characteristics (n=1.0, φn=0.62eV) were demonstrated. Moreover, the electrical characteristics did not deteriorate after post-annealing (400oC, 1h), which guaranteed the thermal stability of Fe3Si/Si structures up to 400oC.

Effects of Fe/Si ratio and growth temperature were investigated in order to realize high quality Fe3Si/Ge structures. It was found that very small Xmin values (2-3%) were achieved in a wide temperature range of 60-200°C under the stoichiometric condition. From TEM observation, it was rvealed that the Fe3Si/Ge structures with atomically flat interfaces were realized. In addition, thermal stability of the Fe3Si/Ge structures was guaranteed up to 400°C. These results suggested that growth at a low temperature (

High-performance poly-Ge thin-film transistors (TFTs) were fabricated using NiGe Schottky contacts as source/drain (S/D). First, formation of NiGe layers by annealing of Ni/n-Ge structures was investigated as a function of annealing temperature, and NiGe/n-Ge Schottky contacts (Φ Bn =0.51 eV) with a low reverse leakage current (∼10 -2 A/cm 2 ) were realized at 200-300°C. On the basis of the results, NiGe Schottky S/D contacts were fabricated using poly-Ge/quartz substrates. The TFTs showed good operation characteristics with a hole mobility of ∼140cm 2 V 1 s 1 . This is a great advantage for the realization of high-performance TFTs for future system-in-displays.

Our recent progresses in epitaxial growth of Fe3Si on Ge substrates are reviewed. Single crystalline Fe3Si layers with atomically flat interfaces were achieved on Ge(111) substrates by optimizing growth conditions at low temperatures (60-200oC). Thermal stability of it was guaranteed up to 400oC. In addition, epitaxial growth of mixed layers composed of Fe3Si, FeGe, and FeSi on Ge substrates at 400oC is reported. Finally, epitaxial growth of Fe3Si/Ge/Fe3Si/Ge structures is discussed. These results will be a powerful tool to open up SiGe related spintronics.

The fabrication of Ge-channel thin-film transistors (TFTs) with Schottky source/drain (S/D) contacts was investigated. First, the annealing characteristics of Ni/c-Ge stacked structures were examined. NiGe/n-Ge Schottky contacts (Bn=0.51 eV, n=1) with a low reverse leakage current [(2–5)×10-2 A/cm2] were obtained at 200–300 °C. Second, the electrical characteristics of Al/SiO2/c-Ge metal–oxide–semiconductor (MOS) structures were investigated, in which SiO2 films were formed by plasma-enhanced chemical vapor deposition at 250 °C. The MOS structures were proven acceptable for device operation. On the basis of the obtained results, TFTs with NiGe Schottky S/D contacts were fabricated using poly-Ge/quartz substrates. The maximum processing temperature was 500 °C in the solid-phase crystallization of a-Ge films. The TFTs showed good p-channel operation characteristics with a mobility of ~100 cm2 V-1 s-1 without showing kink effects. This is a great advantage for the realization of high-performance TFTs for system-in-displays.

Orientation-controlled large-grain (≥10 µm) crystal, i.e., quasi-single crystal, Ge-rich (≥50%) SiGe on insulator grown at low temperatures (≤300 °C) are desired for realization of high-performance flexible electronics. To achieve this, the Au-induced crystallization technique using a-SiGe/Au stacked structures has been developed. This enables formation of (111)-oriented large-grain (≥10 µm) Si1− x Ge x (x ≥ 0.5) crystals on insulating substrates at low temperatures (300 °C). The surface layers of the grown SiGe crystals have uniform lateral composition profiles. By using this technique, formation of quasi-single crystal Ge on flexible plastic sheets is demonstrated. This technique will be useful to realize high-performance flexible electronics.

Development of high-mobility semiconductors is strongly needed to realize high-performance thin-film transistors. To achieve this, we have been investigating low temperature solid-phase crystallization and metal-induced lateral crystallization of a- SiGe on insulating substrates. These realize uniform crystal growth of SiGe with all Ge fractions. In addition, thin-film transistors with Schottky source and drain structures were fabricated, which showed good ambipolar operation characteristics. Present paper reviews such our recent progress of low temperature SiGe growth and discusses the possible application to thin-film transistors with high speed operation.

The low-temperature ( 2000 V/cm). These new findings will be a powerful tool for achieving new poly-SiGe with highly controlled crystal structures.

Thin-film transistors (TFTs) with Schottky source/drain (S/D) structures were fabricated using NiSi and laser-annealed polycrystalline silicon (poly-Si) as Schottky barrier metals and active layers, respectively. The whole fabrication process was performed at low temperatures (

A novel flash memory which has FePt magnetic floating gate was proposed. An FePt magnetic floating gate with a high coercivity was successfully fabricated by DC magnetron sputtering with rapid thermal annealing. As for magnetic properties, the switching magnetic fields of 21 Oe for the NiFe film and 1600 Oe for the FePt film were employed for the control gate and the floating gate materials, respectively. The fundamental characteristics of the magnetic flash memory were confirmed using magnetic metal oxide semiconductor (MOS) capacitor devices and magnetic tunneling diode (MTD) devices.

Pulsed-XeCl excimer laser crystallization of germanium (Ge) and silicon–germanium (SiGe) alloy films formed on quartz glass substrates was investigated. The transient conductance measurements reveled that germanium films were rapidly melted and solidified because of low latent heat compared to silicon films. Formation of silicon–germanium alloy was also observed in the case of laser annealing the Ge/Si layered structure. The crystalline volume ratio was estimated almost 1.0 for Si0.4Ge0.6 films because of small disordered electronic states at grain boundaries, while it was 0.85 for Si films. D 2005 Elsevier B.V. All rights reserved.

Metal-induced lateral crystallization of amorphous Si has been investigated under a wide range of electric fields (0–4000 V/cm). In the low field region ( 2000 V/cm), directional growth aligned to the electric field was observed. This new findings will be a powerful tool to achieve new poly Si with highly controlled structures.

Ge-on-insulator (GOI) having laterally-graded doping-profiles is essential to formation of functional-devices such as high-efficiency thermo-electric devices. To achieve this, rapid-melting growth of a-Ge strips implanted with P ions is investigated under a dose range of 1 × 1012 − 2 × 1015 cm−2. For dose over 1 × 1014 cm−2, grown-Ge layers show n-type conduction. Moreover, for dose of 2 × 1015 cm−2, a laterally-graded doping-profile (~8 × 1015 cm−3/μm) is achieved in the grown region (growth-distance: 0–300 μm) by P segregation during the melt-back process. The graded doping-profile generates electric-fields of ~0.6 V/cm, which can be increased by decreasing strip-length. This technique is expected to facilitate integration of functional-devices on Si-platform.

Low-temperature (~ 250 °C) layer exchange crystallization of poly-Si1 − xGex (x = 1–0) films on insulators has been investigated for realization of advanced flexible devices. We propose utilization of Au as catalyst to enhance the crystallization at low temperatures. By annealing (~ 250 °C, 20 h) of the a-Si1 − xGex (x = 1–0)/Au stacked structures formed on insulating substrates, the SiGe and Au layers exchange their positions, and Au/poly-SiGe stacked structures are obtained. The Ge fractions of the obtained poly-SiGe layers are identical to that of the initial a-SiGe layers, and there is no Si or Ge segregation. This low temperature crystallization technique enables poly-SiGe films on plastic substrates, which are essential to realize advanced flexible devices.

Strain-induced enhancement of carrier mobility is essential for achieving high-speed transistors. The effects of thermal-annealing (temperature: 400–1150 °C) and ultraviolet (UV) laser-annealing (wavelength: 248 nm, temperature: 30–400 °C) on strain-enhancement in Si-pillars covered with Si3N4 stress-liners by plasma-enhanced chemical vapor deposition are investigated. Before annealing, the Si3N4 stress-liners induce a tensile strain (~ 0.5%) in Si. After thermal-annealing (> 800 °C), the strain becomes highly compressive (> ~ 0.4%), because of dehydrogenation-induced structural relaxation in Si3N4 films. On the other hand, the tensile strain becomes large (>~0.7%) after UV laser-annealing at 400 °C, due to non-equilibrium dehydrogenation in Si3N4 films. This strain-enhancement technique is useful for the realization of advanced high-speed three-dimensional transistors.

Low temperature (8%) on insulating substrates is essential to realize next generation flexible electronics. To achieve this, a growth method of high quality GeSn films on insulating substrates by combination of laser irradiation and subsequent thermal annealing is developed. Here, the laser fluence is chosen as weak, which is below the critical fluence for crystallization of GeSn. It is clarified that for samples irradiated with weak laser fluence, complete crystallization of GeSn films is achieved by subsequent thermal annealing at ∼170 oC without incubation time. In addition, the quality of GeSn films obtained by this method is higher compared with conventional growth techniques such as melting growth by pulsed laser annealing or solid-phase crystallization (SPC) without pre-laser irradiation. Substitutional Sn concentrations in the grown layers estimated by Raman spectroscopy measurements are 8-10%, which far exceed thermal equilibrium solid-solubility of Sn in Ge (∼2%). These phenomena are explained by generation of a limited number of nuclei by weak laser irradiation and lateral SPC by subsequent thermal annealing. This method will facilitate realization of next-generation high performance devices on flexible insulating substrates.

Recent progress in the crystal growth of group-IV-based semiconductor-on-insulators is reviewed from physical and technological viewpoints. Liquid-phase growth based on SiGe-mixing-triggered rapid-melting growth enables formation of hybrid (100) (110) (111)-orientation Ge-on-insulator (GOI) structures, which show defect-free GOI with very high carrier mobility (~1040 cm2 V−1 s−1). Additionally, SiGe mixed-crystals with laterally uniform composition were obtained by eliminating segregation phenomena during the melt-back process. Low-temperature solid-phase growth has been explored by combining this process with ion-beam irradiation, additional doping of group-IV elements, metal induced lateral crystallization with/without electric field, and metal-induced layer exchange crystallization. These efforts have enabled crystal growth on insulators below 400 °C, achieving high carrier mobility (160–320 cm2 V−1 s−1). Moreover, orientation-controlled SiGe and Ge films on insulators have been obtained below the softening temperatures of conventional plastic films (~300 °C). Detailed characterization provides an understanding of physical phenomena behind these crystal growth techniques. Applying these methods when fabricating next-generation electronics is also discussed.

Development of a low-temperature (≤250°C) formation technique of orientation-controlled large-grain (

By an insertion of a Ge(Sn) layer and its CMP treatments, we have improved the crystalline and magnetic characteristics of one of the Heusler-compounds, Fe 3 Si, on (111)-oriented Ge on a flexible substrate. This work is a first step of high-performance flexible spintronics for flexible system-in-display devices.

A rapid melting growth technique of amorphous Ge has been developed by using polycrystalline Si islands as growth-seed. High quality single-crystal Ge stripes with 400 μm length, dominantly (100) oriented, are obtained on quartz substrate, which provides a high carrier mobility of 1040 cm 2 /Vs. This technique is expected to be useful to realize Ge-channel thin film transistors with high carrier mobility.

Modulation-doped SiGe/Si/SiGe heterostructures were grown by molecular-beam epitaxy (MBE), and n-type field-effect transistors were fabricated. Electrons transferred to the strained-Si channel increased the electron density to up to 1×10 12 cm −2 with increasing gate voltage, then excess electrons remained in the SiGe doping layer under a higher gate voltage. A device simulation explained this phenomenon well and suggested that device performance can be improved by increasing the Ge content in the SiGe layer to ∼0.5.

To fabricate high quality SiGe/Si heterostructures, control of intermixing between Si and Ge is essential during crystal growth. This paper describes the recent progress of ‘intermixing-controlled epitaxy’. A combined method of MBE (molecular beam epitaxy) and SPE (solid-phase epitaxy) was developed and used to fabricate a new heterostructure (n-Si0.8Ge0.2/Si channel/Si1 − xGexbuffer layer/Si substrate). Observation by TEM demonstrated that the hetero-interface obtained by SPE was atomically flat. This interface provides the ultrahigh mobility of a two-dimensional electron gas (2DEG). In addition, the influence of atomic-hydrogen irradiation during MBE on Ge dispersion in the SiGe mixed crystal is examined. Results indicate that the number of Ge–Ge pairings was decreased by hydrogen irradiation. Such a decrease deformed the local symmetry of the Si–Ge bond from tetrahedral symmetry. As a result, photoluminescence intensity was sucessfully increased.

Molecular beam epitaxy of the ferromagnetic silicide Fe 3 Si on Ge and Si substrates was investigated in a wide temperature range (60–400 °C). Epitaxial growth of Fe 3 Si layers was achieved on Ge (110), Ge (111), and Si (111) substrates. Especially, very low value (2.2%) of the minimum scattering yield in RBS measurements was obtained from Fe 3 Si layers, which were grown on Ge (111) at low temperature (60–130 °C) under the stoichiometric condition (Fe:Si = 3:1). Transmission electron microscopy measurements confirmed the formation of DO3-type Fe 3 Si and atomically flat interface between Fe 3 Si and Ge (111). In addition, thermal stability of Fe 3 Si was guaranteed up to 300 °C. Such high quality Fe 3 Si on Ge (111) substrates can be employed to realize Ge channel spin transistors, which can be integrated with Si large-scale integrated circuits.

Direct formation of strained Si on insulator has been investigated by using laser annealing. The silicon on insulator (SOI) and amorphous Si layers deposited on SOI substrates were irradiated with an excimer laser. After the laser annealing, crystal Si layers with a strain of ∼0.6% were successfully formed on the buried oxide. Spectroscopic ellipsometry and atomic force microscopy measurements revealed the high crystallinity (∼100%) and small surface roughness (∼0.64 nm) of the formed layers. These results demonstrate that laser annealing technique will be a useful tool to fabricate strained Si on insulator without SiGe buffer layers.