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A novel two step etch process using the Bosch-etch mechanism to prevent notching on an SOI wafer is presented. The first etch step is used to attain the maximum etch depth with high etch rate and stop before the buried oxide (BOX). Followed by the second etch step with lower etch rate and tuned to soft land on the BOX to etch the remaining depth. In addition to that it is tailored to also provide a tapered etch profile which is beneficial in reducing the notch if over etching occurs.

In this paper, a novel compliant chip-to-package interconnect, planar microspring, is presented in terms of design consideration, wafer-level fabrication process and mechanical characterization. Several spring designs have been evaluated, and results indicate that a J-shaped spring design produces a combination of high 3D compliances and acceptable electrical parasitics. Further, numerical analyses on the J -shaped microspring interconnect examined the dependence of mechanical and electrical performance upon geometry parameters. A wafer-level fabrication flow combining complementary metal oxide semiconductor (CMOS) back-end-of-line (BEOL) process and 3-D surface micromachining technique has been successfully implemented to create planar microspring interconnect prototypes with a fine pitch (100 mum). The mechanical robustness of the prototype interconnects have been evaluated by nanoindentation. Finally, high-frequency electrical simulation suggested that the interconnect application can be extended up to ~35 GHz without significant power loss.

Stacking of many functional chips in a 3-D stack package leads to high heat dissipation. Therefore, a new platform technology is required to assemble chips vertically and remove the heat effectively. A 3-D stacked package with silicon interposers was developed to integrate one ASIC and two memory chips in a package. Electrical connections in the silicon interposer were formed by through silicon via. Silicon interposer has much high thermal conductivity than organic interposer, therefore the package thermal resistance is lower. Thermal performances of the 3-D package were analyzed and thermal enhancements like thermal via, thermal bridging were evaluated. The designed package showed 5 times lesser thermal resistance compared to a similar package with organic substrate. An additional silicon heat spreader was designed and attached to the package for high power application. Thermal analysis was performed to optimize package thermal performances and experimental validation was carried out. The designed 3-D stack package is suitable for 20 W application.

A novel dual-etch process technology has been developed for the tapering of deep silicon vias which can be used in the fabrication of through-silicon interconnected silicon carriers for 3D system in packaging application. The process consists of two etching steps viz. an anisotropic etch process followed by a global isotropic etch process which causes the vias profile to taper. The 1st etching step is designed to provide high etch rate and throughput while the 2nd etch step is designed to control the taper angle of the via. It has been shown that through this approach of partitioning the via formation process into an anisotropic etch and an isotropic etch process, it is possible to maintain high overall etch rates without compromising on the final via profile and throughput. The via profile achieved has been extensively characterized with respect wide range of critical process parameters and via geometries. It has been demonstrated that regardless of the choice of via formation method, it is feasible to achieve a controllable via taper to realize a void-free copper via-filling by electroplating process.

A low temperature resist trimming process with low trimming rate and good uniformity was developed. Wafer chuck temperature in the ashing chamber was adjusted to be 6 °C to achieve low trimming rate and improve process uniformity. Low power oxygen and argon plasma was used for ashing the resist. Resist lines (0.5 μm wide) patterned with a g-line stepper was trimmed down to sub-100 nm widths. The trimming rate was found to be independent of the initial line width and trimming time. A 0.6 μm CMOS process flow with LOCOS and nitride spacer was suitably modified incorporating resist trimming to fabricate NMOSFETs with gate length as small as 95 nm. Since most polymer-based photoresists can be etched in oxygen plasma, the basic technique could be extended to supplement other lithographic processes for channel length scaling.

This paper describes a process technology to make MEMS devices with laterally integrated polysilicon beam as the structural material instead of single crystal silicon for sensors/ actuators. The process consists of fabricating deep silicon trenches, which are then seamlessly filled with the layers of thermal oxide and polysilicon. The polysilicon on the surface is etched back, leaving behind the polysilicon only inside the trenches. The beams are then released by isotropically etching away the silicon surrounding the polysilicon/ silicon oxide structure. This results in free standing polysilicon beams, which form the MEMS structures. The thermal oxide surrounding the polysilicon can be removed by wet HF etch or by isotropic plasma etch. This process can serve as a general platform for realising various types of high aspect ratio MEMS devices. The various stages of the process development, in realising a low stress polysilicon beams and electrical isolation structures are described in the paper.

In this paper, a method of fabricating radio opaque silicon micro needles for tissue labeling applications is reported. Cylindrical shaped micro needles ranging from 7 × 7 to 11 × 11 arrays with a pitch varying from 60 µm to 100µm are fabricated in silicon using a three step mask process. A backside cavity is generated under DRIE for filling the radiopaque material. Barium sulphate is filled in and a biocompatible sealing is provided to hold the radiopaque material inside. The fabricated needles provide a better contrast enhancement under x-ray imaging.

This paper discusses wafer level vacuum sealing technology with evaporated AuSn solder for a microelectromechanical systems (MEMS) resonator without getter material. The MEMS resonator is fabricated and characterized in a vacuum chamber. Relationship between the Q-factor of the MEMS resonator and the vacuum level is established and used as a reference for later vacuum level calibration. Wafer bonding using evaporated AuSn solder is performed in an EVG wafer bonder. With optimized bonding conditions, the achieved shear strength is higher than 59 MPa and uniform cross-section of the bonding ring has been achieved. The calculated He leakage rate is between 10−13 atm cc/s and 10−14 atm cc/s. By comparing the measured Q-factor of packaged resonator with the reference curve, the corresponding vacuum level is 0.2 Torr. Reliability tests results show that shear strength decreases for 7% and still high enough for real application. The vacuum level after reliability tests is comparable to that of long term vacuum level.

In this paper, Through silicon via (TSV) based interposer fabrication processes for 3D stack packaging has been presented. An interposer test chip of 25 × 25 mm size, has been designed with full array TSVs of 50 um size vias at 300 um pitch. TSVs of aspect ratio 4 are formed on 8 inch wafer using DRIE process and these vias are isolated by thermal oxide, followed by barrier/seed layer of Ti/Cu deposition. TSVs are filled with solid copper (Cu) using optimized pulse reverse damascene electroplating and Cu chemical mechanical polishing (CMP) process also developed to remove the over burden copper with minimum dishing. Multi layer front side metallization process has been demonstrated using electroplated Cu as re-distribution layers (RDL) and spin-on-dielectrics as RDL passivation. Solid Cu filled TSVs are exposed at the backside of the TSVs using backgrinding and Cu CMP. Thin wafer handling process was developed for backside metallization on 200 um thick interposer wafers using support wafer with temporary adhesive bonding. Low temperature dielectric process has been optimized for backside via passivation to isolate the vias from surrounding silicon and backside RDL process as temporary adhesive can not withstand for high temperature processes. The support wafer is de-bonded by sliding at high temperature, followed by cleaning of temporary adhesive material on the front side of interposer wafer using cleaning chemical. TSV interposer of 200um thickness has been fabricated successfully and the vias are in very good connectivity from the top to the bottom. Complete interposer fabrication process issues and solutions have been discussed.

A novel compliant flip-chip interconnect in the form of a planar microspring is presented in this paper. Different spring geometries are evaluated and compared in terms of compliances and electrical parasitics. It is shown that the J-shape spring design gives a better balanced performance. Further numerical studies reveal the geometric dependence of the compliances of J-shape spring interconnects, and also the influence of the sacrificial material upon the electrical performance of the interconnects. The wafer-level process flow for fabrication of the planar microspring interconnects is described and discussed. Prototype interconnects are fabricated by combining planar technology and 3D surface micromachining technology.

A wafer level vacuum package with getters deposited on the cap wafer is developed for an accelerometer device. An accelerometer wafer and cap wafer is bonded together in a vacuum of 1 milli torr and is characterized using a MEMS motion analyzer (MMA). Vacuum inside the package is measured indirectly by measuring the Q factor response of the accelerometer structure inside the package. The obtained results indicated that there is variation from the center to the edge of the wafer. This may be due to difference in the outgassing of the package. Different reliability tests on the wafer level package showed the package is robust to the reliability conditions. A progressive test on Q factor for different cycles of reliability test proven that there is no shift in the measurement value. A 3D wafer level package for accelerometer device is also developed to meet the requirements of vacuum packaging. Hermeticity and CV test showed that no degradation in the device performance when subjected to reliability tests.

A novel dual etch process technology has been demonstrated which provides an opportunity to precisely and independently control the etch throughput and required via slope that is required to achieve conformal deposition of dielectric, copper diffusion barrier and copper seed metallization. It is further shown how a void-free copper via plating has been achieved for implementation into 3-D integrated systems.

A wafer through hole filled via interconnection method on silicon has been developed for 3D wafer level packaging for MEMS (Micrc-Electro mechanical systems) application. In this 3D package the bottom wafer is a MEMS device and the cap wafer is silicon. Using Deep Reactive Ion Etching process the through hole via has been formed on the silicon cap wafer. A conductive material is uniformly deposited on the backside of the cap wafer before the via etch process to serve as an etch stop layer in DRIE (Deep Reactive ion Etching) process. The cap wafer vias are filled with a conducting material by means of electroplating process. The seed metal is usually an UBM (Under bump metallization) layer which is subsequently pattemed to form bond pads on both top and bottom wafers. These two wafers are then aligned and bonded with soldedmetal to form a hermetically sealed wafer level package. Altemate methods are also investigated for plugging the via holes with conducting material and the process has been explained.