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Fabrication cost reduction and performance improvements of state-of-the-art complementary metal–oxide–semiconductor (CMOS) are driving force of device size scaling as well as chip size scaling. To enable continuous device scaling, the device structure was changed from planar field-effect transistors (FETs) to FinFETs shown in Fig. 1 [1] . The FinFETs have the 3D channel shown in Fig. 1 , and it increases on-state current (I on ) per footprint, and suppresses short-channel effects (SCEs) and off-state current (I off ).

For scaling of bulk Si Fin field-effect transistor (FinFET), suppression of short-channel effects is required without ON-state current degradation. In this letter, solid-source doping for channel doping using 1-nm phosphosilicate glass was demonstrated on both p-type (100) Si substrate and p-type bulk Si FinFET. The profile of phosphorus in p-type (100) Si substrate was analyzed by secondary ion mass spectrometry and it was diffused deeper with higher thermal budget of anneal. Fabricated bulk Si FinFETs with using 1-nm phosphosilicate glass showed threshold voltage shift with several anneals at 1- $\mu \text{m}$ and 70-nm gate lengths. Hole mobility at 1- $\mu \text{m}$ gate length and transconductance at 70-nm gate length were also reduced due to increase in impurity concentration of phosphorus diffused by anneals into Fins. Phosphorus diffusion into Fins with using 1-nm phosphosilicate glass was investigated and phosphorus behavior after anneal was clarified by electrical data of p-type bulk Si FinFETs.

Novel device architectures offer improved scalability but come often at the price of increased layout sensitivity and a reduced or changed effectiveness of stressors and gate-last integration schemes. This work focuses on stress effects in n-type FinFETs and p-type Si1-xGex-channel pFETs, and relies mainly on TCAD results. It will be shown that on n-FinFETs, tensile stressed Contact Etch-Stop Layers (t-CESL) are less effective than on planar FETs when a gate-first scheme is used. For gate-last schemes, CESL is as effective as on planar FETs, moreover a strong boost is expected when compared to gate-first schemes. Tensile stressed gates are shown to be an effective stressor on gate-first n-FinFETs, but not on gate-last: in the latter case a slight mobility degradation is predicted. For pFETs with strained Si1-xGex-channels like the Implant-Free Quantum Well (IFQW) FET, it will be shown that elastic relaxation during source/drain recess is an important factor that reduces the effectiveness of Si1 yGey source/drain stressors. For scaled technologies, omitting the source/drain recess altogether and opting for a raised source/drain scheme is preferred. In IFQW pFETs, dependence of the drive current on transistor width is an important concern. It will be shown that a Si1 yGey source/drain reduces the layout dependence of IFQW FETs, an effect that is enhanced further when combined with a gate-last integration scheme.

Ultrathin EOT-values are achieved by using optimized processing conditions and interface layer scavenging in metal-gated (TiN and TaN) HfO"2 based planar and bulk-FinFET devices. EOT values down to 4.5A(T"i"n"v~8.5A) in the planar devices and T"i"n"v

With the continuous down scaling features sizes, the need of speed increase and power consumption reduction start to be more and more critical. The classical integration scheme of poly silicon gate on CMOS devices does not meet the requirements of the 45 nm technology node and beyond. On this matter, new materials and different integration flows are being investigated in order to improve the device performance. High-k materials associated with metals are actively investigated as new gate materials in which different integration approaches like metal gate first or metal gate last are proposed [1].

A comparison between atomic layer chemical vapor deposition (ALCVD) and metal organic chemical vapor deposition (MOCVD) HfO2 layers on Ge indicate that ALCVD layers have some improved capacitor characteristics. An NH3 pre-treatment was essential to obtain MOS C–V characteristics for the deposited HfO2 layer. We also report for the first time, deep sub-micron Ge pFETs made in a silicon-like process flow with a directly etched metal gate stack on a HfO2 dielectric. The results indicate that for improving Ge devices, more understanding on the dopant diffusion control and the reduction of interface state density will be necessary.

As CMOS technology goes into the nanoscale regime, the impact of layout on the device performance becomes increasingly important. In this paper, we propose a physics-based analytical model for Layout Dependent Effects (LDE) due to shallow trench isolation (STI) stress in 28 nm technology using “gate-last” process (Replacement Gate — RMG). The impact of active size and active width are considered and the model links between stress and device parameters such as the mobility and threshold voltage. The model is validated with experimental data. In addition, we investigate the impact of embedded Silicon-Germanium source/drain (eSiGe S/D) stressors in PMOS. Stronger mobility degradation is predicted for small width devices once eSiGe S/D is used. It results in a larger drop of normalized current (μA/μm) (−16%) once compared to transistors without eSiGe (−7%).

A P-SiC (Phosphorus doped Si 1−x C x ) SD (Source Drain) was developed on bulk-Si based nMOS FinFETs (n-FinFETs). P-SiC epitaxial growth on SD provides strain to boost n-FinFET mobility and drive current. Combination of LA (Laser Anneal) and low temperature RTA recovers P-SiC and PSi (Phosphorus doped Si, Si 1-x P x ) strain. A SiGe clad channel on pMOS FinFETs (p-FinFETs) was investigated. Narrower Si fin and SiGe epitaxial growth on fins increase mobility and drive current, which is based on the same carrier transport mechanism as conventional phonon scattering without velocity overshoot around 14nm node.

With the continued scaling of CMOS devices down to 32nm node and beyond, device performance is very sensitive to the lateral diffusion mechanisms influencing the effective channel length. Tools are thus, required to measure with sufficient resolution and accuracy the carrier distribution. Scanning spreading resistance microscopy (SSRM) has evolved as a successful carrier-profiling technique with sub-nm resolution, less than 2 nm/decade gradient resolution and high dynamic range 1015 to 1021 cm−3. In this work, we present the approaches (methodology and special test structures) to obtain a 3D-carrier concentration map for FinFET-based devices. We also correlate the results obtained with SSRM for various process conditions and its implications on device performance.

In this work, we demonstrate for the first time 3D-carrier profiling in FinFETs with nm-spatial resolution using SSRM. The results provide information on gate underlap, dopant conformality, source/drain doping profiles. The 3D-carrier profiles as extracted for two different device approaches (extensions vs. extension-less) are conclusive in demonstrating the differences in device performance and are consistent with first order 3D-simulations.

FinFET is a promising device structure for scaled CMOS logic/memory applications in 22 nm technology and beyond, thanks to its good short channel effect (SCE) controllability and its small variability. Scaled SRAM and analog circuit are promising candidates for finFET applications and some demonstrations for them are already reported. On the other hand, for finFETs production, quite a lot of process challenges are required due to difficult fin/gate patterning in the 3D structure, conformal doping to fin and high access resistance in extremely thin body, etc. The fin/gate patterning can be improved by optimization of patterning stack, patterning scheme and etch chemistry. Alternative doping techniques show good conformal doping in 3D structure in finFETs. High access resistance is reduced by junction optimization and strain boaster technique.

This paper is the first to provide a comprehensive study on the layout dependence of scaled Si 1−x Ge x -channel pFETs.

3D integration has the potential to alleviate the performance limitations that CMOS scaling is facing provided that it preserves the integrity of both front end and back end devices and constituting materials. The impact of wafer thinning and of the proximity of through silicon via on active devices, back end structures, ring oscillators and mixed signal circuit are reported for the first time for a High-k/Metal Gate first strained CMOS technology with low-k BEOL. The relative stress induced by the STI and the TSV are measured by micro-Raman spectroscopy. The measured impact of the stress on a sensitive DAC circuit is used to define a safe keep out area.

This paper provides a comprehensive study of the abnormal PBTI behaviors recently observed in La/Dy-capped high-k films in low-VT nMOSFETs. We found that process details in thermal budget (or dielectric intermixing) and oxygen content of the metal trigger the onset of these abnormalities. The DeltaVT relaxation during the PBTI recovery period induced by bulk trapping/de-trapping is believed to be oxygen vacancies related, and can be suppressed either by reducing dielectric intermixing with lower laser anneal powers (La above or below HK), or by increasing the oxygen concentration, i.e., TaCNO metal electrode instead of TaCN (La above HK). Putting La below HK can result in a similar VT tune-ability with less thermal budget for intermixing with the IL (with superior PBTI), without loss of current drive-ability. We propose Ta2C/HK/LaO/IL + LLP anneals as an optimum nFETs stack configuration for practical CMOS integration.

We demonstrate for the first time CMOS integration of dual WF (work function) metal gates on HfSiON using Ni-phase controlled FUSI. The novel integration scheme that we demonstrate uses our optimized 2-step Ni FUSI process (1) for simultaneous full silicidation of nMOS and pMOS, achieving different Ni/Si ratios on nMOS and pMOS by reduction of the pMOS poly height through a selective and controlled poly etch back prior to gate silicidation. This novel integration scheme offers the advantages of 1) simplicity (same Ni deposition and silicidation process on nMOS and pMOS), 2) large process window for poly etch-back process (same pMOS characteristics for poly thickness variation of 50%), 3) WF and Vt tuning on HfSiON by phase control, with 4) scalable, linewidth independent suitable Vt's for nMOS (0.5 V) and pMOS (-0.3 V), and 5) solves process yield issues of Ni-rich silicides related to volume expansion, stress, filaments and voiding, resulting in a continuous silicide that is nicely confined between the sidewall spacers. Ring oscillator operation was also demonstrated

In this paper, we investigate the impact of replacing tungsten (W) by a Cu-based contact module. Our experiments show that a 50% reduction in contact resistance can be obtained. This is attributed to both the choice of barrier as well as filling material. An increased drive current is measured on narrow transistors with single contacts. The intrinsic gate oxide reliability is not compromised. Results on demonstrator ring oscillator structures show how the parasitic contribution to the transistor series resistance will increasingly impact circuit delay and power dissipation upon scaling. Cu is presented as a viable solution to postpone these effects by at least one node

This work presents the first comprehensive evaluation of the manufacturability and reliability of dual WF phase controlled Ni-FUSI/HfSiON CMOS (NMOS: NiSi; PMOS: Ni2Si and Ni31 Si12 evaluated) for the 45 nm node. RTP1 and poly/spacer height were identified as the most critical process control parameters in our flow. We demonstrate that a novel sacrificial SiGe cap addition to the flow (improved poly-Si/spacer height control) opens the RTP1 process window from ~5degC to ~20degC for gate lengths down to 45nm, making scalable dual WF CMOS Ni-FUSI manufacturable. We demonstrate Vt control with sigma~19mV (including wafer to wafer variation, N=1000, 45 nm devices) for NMOS (NiSi), and sigma~21mV for PMOS. TDDB and NBTI reliability evaluation of NiSi and, for the first time, of Ni2Si and Ni31Si12 was done. ~1V or larger operating voltages (Vop) were extrapolated for a 10 years lifetime. Using a higher back-end thermal budget showed no reliability degradation

We demonstrate for the first time the scalability of NiSi and Ni/sub 3/Si FUSI gate processes down to 30 nm gate lengths, with linewidth independent phase and V/sub t/ control. We show that 1-step FUSI is inadequate for NiSi FUSI gates, because it results in incomplete silicidation at low thermal budgets or in a linewidth dependent Ni silicide phase - inducing V/sub t/ shifts - at higher thermal budgets. We show that V/sub t/ and WF shifts are larger on high-K (HfO/sub 2/ (250 mV) or HfSiON (330mV)) than on SiON (110mV) and report Fermi level unpinning for Ni-rich FUSI on high-K. In contrast, we demonstrate the scalability of Ni/sub 3/Si FUSI, with no phase control issues, and report HfSiON Ni/sub 3/Si FUSI PMOS devices with V/sub t/= -0.33 V. Lastly, we show that, for NiSi, phase control down to narrow gate lengths can be obtained with a 2-step FUSI process.