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Stacked chip is the one of the candidate structure to realize low on-resistance, small package. In order to minimize the chip size, it is required to overlap two gate and two source electrodes between two stacked chips, respectively. However, it is impossible to overlap them when wire bonding are used. We completely overlapped these electrodes between two chips by Cu clips. Additionally, double side 20µm Cu plating was applied to the device in order to obtain higher avalanche capable current density of the stacked chip. In this paper, the demonstration results of the chip by using new process are described.

We investigated characteristics impact of alpha-particles irradiation to power MOSFETs and demonstrated alpha-particle shielding effect of thick copper plating film on a power MOSFET. We used americium-241 alpha-source for irradiating alpha-particles to the surface of the power MOSFET die. Irradiation under gate-source bias caused threshold voltage (Vth) decrease due to generated trapped holes in gate oxide, however, no Vth shift occurred under drain–source bias. We found that sensitivity to alpha-particles depends on gate structures of trench or planar. Recovery behavior of Vth shift by gate bias or thermal annealing support the hole trapping model in the gate oxide. We evaluated alpha-particle shielding effect of thick copper plating film. We demonstrated more than 15 micrometer thick copper plating on the power MOSFET shielded alpha-particles successfully.

Frequency dependent properties of accumulation-mode MOS varactors, which are key elements in many RF circuits, are dominated by Non-Quasi-Static (NQS) effects in the carrier transport. The circuit performances containing MOS varactors can hardly be reproduced without considering the NQS effect in MOS-varactor models. For the LC-VCO circuit as an example it is verified that frequency-tuning range and oscillation amplitude can be overestimated by over 20% and more than a factor 2, respectively, without inclusion of the NQS effect.

Non-linearity of metal oxide semiconductor field-effect transistor (MOSFET) characteristics induces harmonic distortions, which causes serious problems for RF analog applications. Features of the harmonic distortions are investigated experimentally under high frequency operations. Comparison of measured harmonic distortions with inter-modulation distortions concludes that the harmonic distortions are frequency dependent under high frequency operations. A reason for this is enhanced contribution of the displacement, which is originally frequency dependent.

We have developed a surface-potential-based metal–oxide–silicon (MOS)-varactor model valid for RF applications up to 200 GHz. The model enables the calculation of the MOS-varactor capacitance seamlessly from the depletion region to the accumulation region and explicitly considers the carrier-response delay causing a non-quasi-static (NQS) effect. It has been observed that capacitance reduction due to this non-quasi-static effect limits the MOS-varactor application to an RF regime.

Back Side Illumination (BSI) CMOS image sensors with two-layer photo detectors (2LPDs) have been fabricated and evaluated. The test pixel array has green pixels (2.2um x 2.2um) and a magenta pixel (2.2um x 4.4um). The green pixel has a single-layer photo detector (1LPD). The magenta pixel has a 2LPD and a vertical charge transfer (VCT) path to contact a back side photo detector. The 2LPD and the VCT were implemented by high-energy ion implantation from the circuit side. Measured spectral response curves from the 2LPDs fitted well with those estimated based on light-absorption theory for Silicon detectors. Our measurement results show that the keys to realize the 2LPD in BSI are; (1) the reduction of crosstalk to the VCT from adjacent pixels and (2) controlling the backside photo detector thickness variance to reduce color signal variations.

The dc and RF analog characteristics of ultrathin gate oxide CMOS on [110] surface-oriented Si substrates were investigated for the first time. The transconductance of p-MOSFETs on [110] substrates is 1.9 times greater than that on [100] substrates even in gate oxides in the direct-tunneling regime. An extremely high cutoff frequency of 110 GHz was obtained in 0.11 /spl mu/m gate length p-MOSFETs with 1.5 nm gate oxides. This is the highest value ever obtained for p-channel Si MOSFETs at room temperature. Further, it was demonstrated that more than 100 GHz of cutoff frequency is realized both for n- and p-MOSFETs. Thus, using [110] substrates results in a better balance for n- and p-MOS performances. The SiO/sub 2/ film and SiO/sub 2//Si interface qualities on [110] substrates were also investigated. In this experiment, it was found that direct-tunneling gate leakage current and initial 1/f noise of MOSFETs on [110] substrates are larger than those on [100] substrates. The reliability regarding Negative Bias Temperature Instability (NBTI) for p-MOSFETs on [110] substrates was also inferior to that for [100] MOSFETs. However, with a high-k insulator or improvement of the SiO/sub 2/ film quality, high mobility of p-MOSFETs on [110] substrates will have a potential not only for digital applications but also for new RF analog circuits under low supply voltage.

The properties of ultrathin gate oxides in the direct-tunneling regime and the characteristics of the related CMOS transistors on a [111] surface-oriented Si substrate were investigated and compared with those on a [100] substrate for the first time. It was confirmed that low field mobility of n-MOSFETs on the [111] substrate is smaller than that on the [100] substrate and that of p-MOSFETs on [111] is larger than that on [100] until the direct-tunneling gate oxide regime. It has been found that most of the electrical properties of MOSFETs, with the notable exception of mobility, become almost identical for [100] and [111] substrates when the oxide thickness is reduced to less than 2.0 nm. Some of the properties are quite different between the two substrates for the thicker oxide case. It has been found that the reliability of hot carrier injection and time-dependent dielectric breakdown (TDDB) of the oxides and MOSFETs on the [111] substrate is slightly better than that on the [100] substrate. In addition, the characteristics and reliability of oxides and MOSFETs on a wafer tilted 4/spl deg/ from [100] axis were investigated. It was found that there are few differences in the mobility between [100] and [100] 4/spl deg/ off substrates for both n- and p-MOSFET cases. The reliability of oxides or MOSFETs on the wafer was identical to that on normal [100] substrate. These results suggest that ultrathin gate oxide MOSFETs on Si surfaces with various orientations are likely to have practical applications. This is good news for possible future new structures of MOSFETs such as vertical or three-dimensional (3-D) MOSFETs.

Salicide is one of the indispensable techniques for high-performance logic devices and its importance increases as the device dimensions become small towards sub-100 nm and hence, the source/drain sheet resistance becomes large. TiSi2 used popularly as the silicide material has been eventually replaced by CoSi2, because of its relatively stable nature during the salicide process. For sub-100-nm technology node, CoSi2 is expected to be further replaced by NiSi. NiSi has several advantages over TiSi2 and CoSi2 for the ultra-small CMOS process. They are (1) low temperature silicidation process, (2) low silicon consumption, (3) no bridging failure property, (4) smaller mechanical stress, (5) no adverse narrow line effect on sheet resistance, (6) smaller contact resistance for both n- and p-Si, and (7) higher activation rate of B for SiGe poly gate electrode. In this paper, NiSi salicide technology is explained.

The nondoped selective epitaxial Si channel technique has been applied to ultrathin gate oxide CMOS transistors. It was confirmed that drain current drive and transconductance are improved in the epitaxial channel MOSFETs with ultrathin gate oxides in the direct-tunneling regime. It was also found that the epitaxial Si channel noticeably reduces the direct-tunneling gate leakage current. The relation between channel impurity concentration and direct-tunneling gate leakage current was investigated in detail. It was confirmed that the lower leakage current in epitaxial channel devices was not completely explained by the lower impurity concentration in the channel. The results suggest that the improved leakage current in the epitaxial channel case is attributable to the improvement of some aspect of the oxide film quality, such as roughness or defect density, and that the improvement of the oxide film quality is essential for ultrathin gate oxide CMOS. AFM and 1/f noise results support that SiO/sub 2/-Si interface quality in epitaxial Si channel MOSFETs is improved. Good performance and lower leakage current of TiN gate electrode CMOS was also demonstrated.

The high-frequency AC characteristics of 1.5-nm direct-tunneling gate SiO/sub 2/ CMOS are described. Very high cutoff frequencies of 170 GHz and 235 GHz were obtained for 0.08-/spl mu/m and 0.06-/spl mu/m gate length nMOSFETs at room temperature. Cutoff frequency of 65 GHz was obtained for 0.15-/spl mu/m gate length pMOSFETs using 1.5-nm gate SiO/sub 2/ for the first time. The normal oscillations of the 1.5-nm gate SiO/sub 2/ CMOS ring oscillators were also confirmed. In addition, this paper investigates the cutoff frequency and propagation delay time in recent small-geometry CMOS and discusses the effect of gate oxide thinning. The importance of reducing the gate oxide thickness in the direct-tunneling regime is discussed for sub-0.1-/spl mu/m gate length CMOS in terms of high-frequency, high-speed operation.

Hot-carrier degradation on electrical characteristics of MOSFETs in the direct-tunneling regime of the gate oxide was investigated under a wide range of conditions, namely stress bias, oxide thickness, gate length, and channel-type dependence. It was confirmed that the transconductance degradation of n-MOSFETs with thinner gate oxides is smaller than that of thicker gate oxide MOSFETs, in spite of larger gate direct-tunneling leakage current and larger hot-carrier generation. For p-MOSFETs, little degradation was observed under all conditions of stress bias, oxide thickness, and gate length.

A design method for RF power Si-MOSFETs suitable for low-voltage operation with high power-added efficiency is presented. In our experiments, supply voltages from 1 V to 3 V are examined. As the supply voltage is decreased, degradation of transconductance also takes place. However, this problem is overcome, even at extremely low supply voltages, by adopting a short gate length and also increasing the N/sup -/ extension impurity concentration-which determines the source-drain breakdown voltage (V/sub dss/)-and thinning the gate oxide-which determines the TDDB between gate and drain. Additionally, in order to reduce gate resistance, the Co-salicide process is adopted instead of metal gates. With salicide gates, a 0.2 /spl mu/m gate length is easily achieved by poly Si RIE etching, while if metal gates were chosen, the metal film itself would have to be etched by RIE and it would be difficult to achieve such a small gate length. Although the resistance of a Co-salicided gate is higher than that of metal gate, there is no evidence of a difference in power-added efficiency when the finger length is below 100 /spl mu/m. It is demonstrated that 0.2 /spl mu/m gate length Co-salicided Si MOSFETs can achieve a high power-added efficiency of more than 50% in 2 GHz RF operation with an adequate breakdown voltage (V/sub dss/). In particular, an efficiency of more than 50% was confirmed at the very low supply voltage of 1.0 V, as well as at higher supply voltages such as 2 V and 3 V. Small gate length Co-salicided Si-MOSFETs are a good candidate for low-voltage, high-efficiency RF power circuits operating in the 2 GHz range.

We describe the relationship between the sheet resistance of Co-silicided poly-Si and various doping elements. The surface condition of the poly-Si before Co sputtering plays an important role in suppressing the "narrow line effect," in which the silicide sheet resistance degrades as the gate length decreases. Si-O and Si-C bonding takes place in the gate poly-Si during RIE processing for gate side-wall formation when there is no CVD SiO/sub 2/ gate cap. This leads to the sheet resistance degradation of CoS/sub 2/ when the gate length is reduced. The degradation becomes less severe as the weight of the ions implanted during gate poly-Si doping increases, because the bonding is inhibited by heavier ions. The best way to suppress this degradation, however, is to prevent exposure of gate poly-Si surface by implementing a CVD SiO/sub 2/ cap during gate side-wall formation. When this is done, the sheet resistance degradation does not occur even when the gate length is 0.1 /spl mu/m for all types of implanted ions. We also observed thermal stability of the sheet resistance up to 1000/spl deg/C. That can be improved, as well as narrow line effect, by using this cap process. However, the thermal stability of gate oxide TDDB depends on the type of ion implantation. The temperature at which degradation of TDDB begins rises as the weight of the implanted ions increased. This degradation depends on the grain size, and grains increase in size as the weight increases. The highest temperature before the onset of TDDB degradation is seen with in-situ phosphorus-doped n/sup +/ polysilicon, because the grain size is greatest in this case.

A self-Aligned Doped Channel (SADC) is proposed and investigated for the first time. In the SADC process, the channel doping process is carried out by using solid phase diffusion from the gate; hence the doping region is fully self-aligned to the gate, and the junction capacitance can be reduced. In addition, the implantation damage in the channel is reduced. We obtained 0.25 μm gate length nMOSFETs with low noise and low power consumption by using the SADC structure. Hence, this structure is attractive for small geometry RF CMOS devices.

A new process for a counter-doped region suitable for a 0.15 μm (gate length) buried channel (BC) pMOSFET is presented. At present serious short-channel effects of BC p-MOSFETs are recognized broadly as prohibitive for application at 0.1 μm. In order to realize 0.15 μm BC pMOSFETs, we propose a new process step, making use of a boron solid phase diffused channel (SPDC) from a Boron-doped silicate glass (BSG) to form an extremely shallow counter-doped region, which enables suppression of short-channel effects. Devices fabricated in this way exhibit good short-channel behavior at 0.15 μm gate length and, additionally, provide an excellent current driving-ability. Threshold voltage control is easy by optimizing the diffusion condition. We propose SPDC as a suitable process applicable to 0.2–0.1 μm BC p-MOSFET.

An 0.18-/spl mu/m CMOS technology with multi-V/sub th/s for mixed high-speed digital and RF-analog applications has been developed. The V/sub th/s of MOSFETs for digital circuits are 0.4 V for NMOS and -0.4 V for PMOS, respectively. In addition, there are n-MOSFET's with zero-volt-V/sub th/ for RF analog circuits. The zero-volt-V/sub th/ MOSFETs were made by using undoped epitaxial layer for the channel regions. Though the epitaxial film was grown by reduced pressure chemical vapor deposition (RP-CVD) at 750/spl deg/C, the film quality is as good as the bulk silicon because high pre-heating temperature (940/spl deg/C for 30 s) is used in H/sub 2/ atmosphere before the epitaxial growth. The epitaxial channel MOSFET shows higher peak g/sub m/ and f/sub T/ values than those of bulk cases. Furthermore, the g/sub m/ and f/sub T/ values of the epitaxial channel MOSFET show significantly improved performances under the lower supply voltage compared with those of bulk. This is very important for RF analog application for low supply voltage. The undoped-epitaxial-channel MOSFETs with zero-V/sub th/ will become a key to realize high-performance and low-power CMOS devices for mixed digital and RF-analog applications.

A silicided silicon-sidewall source and drain (S/sup 4/D) structure is proposed for sub-0.1-/spl mu/m devices. The merit of the S/sup 4/D structure is that the series resistance of the source and drain is significantly reduced since the silicide layer is attached very close to the gate electrode and the silicon sidewall can be doped very highly. Thus, very high drain current drive can be expected, Another advantage of this structure is that the source and drain extensions are produced by the solid-phase diffusion of boron from the highly doped silicon-sidewall. Thus, shallow extensions with very high doping can be realized. A 75-nm gate length pMOSFET fabricated with this structure is shown to exhibit excellent electrical characteristics.

Although direct tunneling gate oxide MOSFETs are expected to be useful in high-performance applications of future large-scale integrated circuits (LSIs), there are many concerns related to their manufacture. The uniformity, reliability, and dopant penetration of 1.5-nm direct-tunneling gate oxide MOSFETs were investigated for the first time. The variation of oxide thickness in an entire 150-mm wafer was evaluated by TEM and electrical measurements. Satisfactory values of standard deviations in the TEM measurements and threshold voltage measurements for MOSFETs with a gate area of 5 /spl mu/m/spl times/0.75 /spl mu/m, were obtained. These values improved significantly in the case of MOS capacitors with larger gate areas. The oxide breakdown field and the reliability with respect to charge injection were evaluated for the 1.5-nm gate oxides and found to be better than those of thicker gate oxides. Dopant penetration was not observed in n/sup +/ polysilicon gates subjected to RTA at 1050/spl deg/C for 20 s and furnace annealing at 850/spl deg/C for 30 min. Although much more data will be required to judge the manufacturing feasibility, these results suggest that 1.5-nm direct-tunneling oxide MOSFETs are likely to have many practical applications.

Undoped epitaxial channel n-MOSFET with high transconductance was developed. In order to obtain a good crystal quality of the epitaxial layer and, thus, to achieve high performance, it is important to reduce the oxygen concentration at the epitaxial Si/Si substrate interface. In this paper, we describe the relationship between the electrical characteristics and the surface density of oxygen at the epitaxial Si/Si substrate. We also describe the dependence of the electrical characteristics on epitaxial Si thickness. The g/sub m/ of n-MOSFET with 40-nm epitaxial Si for 0.10-/spl mu/m gate length was 630 mS/mm at V/sub d/-1.5 V, and the drain current was 0.77 mA//spl mu/m. This g/sub m/ value in the case of the epitaxial Si channel is about 20% larger than that of bulk the MOSFET. These results show that epitaxial Si channel MOSFET's are useful for future high-speed ULSI devices.

The ability to operate 1.5 nm direct-tunneling gate oxide MOSFETs at low power and high speed with a low supply voltage in the 0.5 V range is investigated. We extrapolate the performance of current high-end MPUs assuming that conventional 0.4 μm MOSFETs are replaced by such direct-tunneling gate oxide MOSFETs. A simple estimate shows that the high current drive of direct-tunneling gate oxide MOSFETs may lead to MPUs which operate at frequencies several times higher than today's, while consuming several times less power.

A silicided silicon-sidewall source and drain (S/sup 4/D) nMOSFET is demonstrated and its hot carrier reliability is investigated for the first time. This S/sup 4/D nMOSFET exhibited high drain current and well-suppressed short channel effects concurrently. In spite of the impact ionization rate issue, the S/sup 4/D structure offers a major improvement in current and transconductance degradations as compared with the LDD structure. The mechanism of the improved hot carrier reliability is explained using a two-dimensional (2-D) simulation.

In this paper, normal operation of a MOSFET with an ultra-thin direct-tunneling gate oxide is reported for the first time. These high current drive n-MOSFET's were fabricated with a 1.5 nm direct-tunneling gate oxide. They operate well at gate lengths of around 0.1 /spl mu/m, because the gate leakage current falls in proportional to the gate length, while the drain current increases in inverse proportion. A current drive of more than 1.0 mA//spl mu/m and a transconductance of more than 1,000 mS/mm were obtained at a gate length of 0.09 /spl mu/m at room temperature. These are the highest values ever obtained with Si MOSFET's at room temperature. Further, hot-carrier reliability is shown to improve as the thickness of the gate oxide is reduced, even in the 1.5 nm case. This work clarifies that excellent performance-a transconductance of over 1,000 mS/mm at room temperature-can be obtained with Si MOSFET's if a high-capacitance gate insulator is used.

The reduction of gate length improves the performance of a MOSFET. However, this is difficult to do when the gate length is less than 0.1 μm for numerous reasons. This paper reports the results of improvement of the MOSFET performance employing various means. It was found that the current drive was only 30 percent higher with a gate length of 40 nm than with a gate length of 0.1 μm. Even when the gate oxide was 1.5 nm, which is half the oxide thickness for a direct tunneling leakage limit, it was found that the MOSFETs operate normally and the current drive was 1.6 times higher than when the gate oxide was 3 nm, because of the increase of gate capacitance. When a low-doped thin Si epitaxial layer was used as the intrinsic channel, the channel drive was improved by 20 percent because of higher carrier mobility, compared with the current-driving efficiency of a MOSFET formed by bulk material. The problem of source drain parasitic resistance increase in small-geometry MOSFETs was solved by using a novel device structure, i.e., S4D. Using this new structure, the parasitic resistance was reduced by one order of magnitude. Combining the aforementioned techniques, the current-driving efficiency could be improved further even when the gate length is in the sub-0.1 μm region.

A nickel-monosilicide (NiSi) technology suitable for a deep sub-micron CMOS process has been developed. It has been confirmed that a nickel film sputtered onto n/sup +/- and p/sup +/-single-silicon and polysilicon substrates is uniformly converted into the mono-silicide (NiSi), without agglomeration, by low-temperature (400-600/spl deg/C) rapid thermal annealing. This method ensures that the silicided layers have low resistivity. Redistribution of dopant atoms at the NiSi-Si interface is minimal, and a high dopant concentration is achieved at the silicide-silicon interface, thus contributing to low contact resistance. This NiSi technology was used in the experimental fabrication of deep-sub-micrometer CMOS structures; the current drivability of both n- and p-MOSFET's was higher than with the conventional titanium salicide process, and ring oscillator constructed with the new MOSFET's also operated at higher speed. >

A contact plug technique employing selective nickel silicidation of polysilicon with a titanium nitride barrier layer has been developed. This technique provides a contact resistance equal to that of an unplugged metal contact, while also realizing the flatness of a polysilicon plug over contact regions. Using this technique, a completely silicided plug for both shallow and deep contact holes can be achieved at the same time. The structure of the plug was analyzed using TEM photography, EDX, and electro-diffraction measurements, and the silicidation stopping ability of the TiN layer was confirmed. The low leakage current of junction diodes and lack of transistor characteristic degradation when using the Ni silicided plug are demonstrations of the integrity of this technique. The results indicate that this technology is suitable for deep-submicrometer ULSIs. >

It is difficult to realize the built-in antenna for wideband systems, because a frequency bandwidth of the low profile antenna is narrow. A frequency tunable antenna is a technique for wideband characteristics. In this paper a low profile double resonance frequency tunable antenna using MEMS variable capacitors is presented. It has high efficiency over a wide frequency band. Through both resonant portions from 465 to 665 MHz, the efficiency of more than −4 dB and the VSWR of less than 3 are observed in the measurement using the variable capacitor of 0.4–0.9 pF.

In this paper, we report a thin-film encapsulation technology for wafer-level micro-electro-mechanical systems (MEMS) variable capacitor package. The electrical characteristics of MEMS are adversely affected by moisture. In order to prevent moisture from permeating into a package, the top surface was protected with a plasma-enhanced chemical vapor deposition (PE-CVD) SiN layer. The developed packages become a hybrid thin-film hermetic encapsulation consisting of an internal shell using PE-CVD SiO, a seal layer coating with resin, and an external protective layer formed by PE-CVD SiN. The process is fully compatible with standard low-cost back-end-of-the-line (BEOL) technologies for LSIs as a wafer-level package (WLP). This hybrid structure was very effective for protecting the MEMS device from external moisture. Moreover, the electrode surface area has to be wide, because a wide range of capacities is necessary in MEMS variable capacitors. We have developed a large (1480 × 1080 µm) hermetic thin-film encapsulation as WLP.

High-resistivity substrate with beyond 1000 ohm-cm realizes high performance in terms of inductor, antenna, MIM capacitor and substrate noise for high- frequency applications. However, this wafer has serious problems for mixed-signal, RF and digital circuits. Those are reduction of high resistivity during sinter process such as 400degC, larger leakage current between nwells, extreme lower snap-back voltage in latch-up behavior and higher RF noise. The RF noise is proportional to square root of Si substrate resistivity in our experience. In this paper, it is shown that these problems can be resolved by the optimum wafer fabrication process and the additional ion implantation.

A 3 V operation RF MEMS variable capacitor using hybrid actuation of piezoelectric and electrostatic forces is presented. Bending of the piezoelectric actuator is controlled by a lithographical pattern formed on top of the actuator. The hybrid actuation and the optimized bending enabled 2.6 V pull- in voltage with the pull-out voltage as high as 2.0 V The measured capacitance ratio is 14.

An RF MEMS variable capacitor using hybrid actuation of piezoelectric and electrostatic forces is presented. A surface micromachining process is used to fabricate the device. The piezoelectric actuator, which uses thin film PZT, enables low voltage actuation while the electrostatic actuator realizes large capacitance ratio. The measured capacitance ratio is Cmax/Cmin=14 at 5V. We demonstrate that the hybrid actuation enables to lower the pull-in voltage without changing the pull-out voltage. We also show that the shift of pull-out voltage due to dielectric charging can be reduced drastically at actuation voltages below 10V. In this sense, the hybrid actuation can realize low voltage operation with enhanced robustness for stiction.

HfSiON is one of the most promising alternative gate dielectric materials for low standby power (LSTP) application. Recently, DC performance, gate leakage current, and reliability have been reported by T. Watanabe et al in 2004. However, study of analog performances of CMOS with HfSiON gate dielectrics is not sufficient. In this paper, we discuss 1/f noise and matching of CMOS with HfSiON gate dielectrics and predict trends in S/sub vg/ with technology scaling according to the ITRS roadmap based on Mikoshiba's model. The HfSiON dielectric condition for mixed signal CMOS were investigated. In order to satisfy 1/f noise (S/sub vg/) requirement from ITRS roadmap beyond hp65nm, the Nt must be below 1.5 /spl times/ 10/sup 17/ cm/sup -3/eV/sup -1/. The results of Vth matching were excellent even when HfSiO gate dielectric was applied to MOSFET.

In this paper, we describe the high analog performance of MOSFETs and inductors on 1.7/spl mu/m ultra-thin chip with permalloy film.

Fully oxygen precipitated (FOP) wafers can suppress slip generation during the STI process and maintain high substrate resistivity. Additional boron implantation can suppress the leakage current between the adjacent wells due to shallow Xj. No effect on MOSFET characteristics by this implantation was observed. The high resistivity substrate (HRS) can provide good ESD performance and suppress the passage of high frequency signals through the substrate in resistors. Thus, HRS with FOP & additional implantation is effective for future mixed signal CMOS with RF circuits.

A non-doped selective epitaxial Si channel technique has been applied to ultra-thin gate oxide CMOS transistors with TiN and polysilicon gate electrodes, and its effect on direct-tunneling gate leakage current has been investigated. It was found that the epitaxial Si channel noticeably reduces the direct-tunneling gate leakage current in both the TiN and polysilicon gate electrode cases. Improved drain current drive and transconductance of the epitaxial channel MOSFETs with ultra-thin gate oxides in the direct-tunneling regime has been also demonstrated.

Using a newly proposed structure of the multi-via MIM capacitor, amorphous Ta/sub 2/O/sub 5/ films were investigated. Amorphous Ta/sub 2/O/sub 5/ with the proposed structure is one of the suitable combinations for the capacitors for RF analog applications.

A contact filling-technique that utilizes polysilicon plug formation followed by Ni silicidation with a TiN barrier at the polysilicon plug bottom is described. Self-aligned complete silicidation of both shallow and deep contacts can be achieved at the same time by using the TiN silicidation stop. By using this technique in place of a polysilicon plug, low contact resistance was achieved for both n/sup +/ and p/sup +/ contacts. A completely silicided plug for both shallow and deep contact holes can be achieved at the same time. The low leakage current of junction diodes and lack of transistor characteristic degradation when using the Ni silicide plug demonstrate the integrity of the technique. >

We have, for the first time, demonstrated silicon MOSFET's with an ultra-thin epitaxial channel grown by low-temperature UHV-CVD; this allows the channel region to be doped with high precision. The boron concentration and epitaxial layer thickness can be chosen independently, so it is easily possible to adjust the threshold voltage of the p-MOSFET's even in the case of n-type polysilicon gates. It was confirmed that choosing an ultra-thin epitaxial layer-in the 10 nm range-leads to suppression of the short-channel effects in n-type polysilicon gate buried-channel MOSFET's, while maintaining an appropriate value of threshold voltage. >

We have presented a design method of RF power Si-MOSFETs for low voltage and high power-added efficiency operation. It has been demonstrated that 0.2 /spl mu/m gate length Co-salicided Si MOSFETs can achieve high power-added efficiency of more than 50% at 2 GHz RF operation with sufficient breakdown voltage (V/sub dss/S) by choosing optimum gate oxide thickness and N/sup -/ extension impurity concentration. Especially, efficiency of more than 50% was confirmed under very low supply voltage of 1.0 V, as well as higher supply voltage such as 2 and 3 V. The small gate length Co salicided Si-MOSFET is a good candidate for low-voltage, high efficiency RF power circuits for 2 GHz operation.

Ultra-high performance n-MOSFETs were fabricated with a tunneling gate oxide 1.5 nm thick. It was found that these devices operate well when the gate length is around 0.1 /spl mu/m, because gate leakage current falls in proportion to the gate length and the drain current increases in inverse proportion. A very high drivability of 1.1 mAspl mu/m at 15 V was obtained, even in devices with a 0.14 pm gate length. A record high transconductance, 1,010 mS/mm at room temperature was also obtained in 0.09 /spl mu/m MOSFETs. Confirmation was obtained that hot-carrier reliability improves as the gate oxide thickness is reduced, even in the 1.5 nm case. High current drive at the low supply voltage of 0.5 V was also demonstrated. We made clear that very high performance is obtained in Si MOSFETs, if we can use a high capacitance gate insulator. In future devices, the tunnel gate oxide may be a good candidate for such a gate film, depending upon their applications. >

The influence of high substrate doping on the characteristics of small-geometry n- and p-MOSFETs down to 0.1 /spl mu/m has been investigated in detail. A practical limiting impurity concentration is found to exist at around 2/spl sim/5/spl times/10/sup 18/ cm/sup -3/ depending upon the application. In addition, unusual behaviors are found in the hot carrier characteristics in the region of high doping concentration. >

We investigated the Diffused shield Under the Oxide (DUO) for the first time. DUO is an extremely shallow diffusion layer in the n-well under the field oxide. DUO can be formed by high energy implantation through the field oxide, and it can be formed by the process of the channel stop implant for MOSFETs simultaneously. Application of DUO provided a 79% improvement in Q-factor and the comparable shield effect on the n-well. This structure is one of the suitable ground shield for the spiral inductor of the rf CMOS.