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Bilayer selectorless resistive random-access memories (RRAM) have been demonstrated by utilizing the intrinsic nonlinear resistive switching (RS) characteristics, without additional transistor or a selector integration. The bilayer structures, i.e. high-k layer/low-k layer stacks, are highly scalable while suppressing the sneak path currents (SPC) and reading error in the crossbar RRAM array. The nonlinearity (NL) modulation is also investigated by different operating schemes, and a multilevel cell application is demonstrated with the current-sweep method. The results provide additional insights into the development and optimization of bilayer selectorless RRAMs with high nonlinearity, good memory window, and low switching energy (∼ 40 pJ/bit), which enable the high-density storage and low-power crossbar array memory applications.

Selectorless graphite-based resistive random-access memory (RRAM) has been demonstrated by utilizing the intrinsic nonlinear resistive switching (RS) characteristics, without an additional selector or transistor for low-power RRAM array application. The low effective dielectric constant value (k) layer of graphite or graphite oxide is utilized, which is beneficial in suppressing sneak-path currents in the crossbar RRAM array. The tail-bits with low nonlinearity can be manipulated by the positive voltage pulse, which in turn can alleviate variability and reliability issues. Our results provide additional insights for built-in nonlinearity in 1R-only selectorless RRAMs, which are applicable to the low-power memory array, ultrahigh density storage, and in-memory neuromorphic computational configurations.

Resistive random access memory (RRAM) using various metal oxides (i.e., SiO2[1], HfO2, NiO[2], Al2O3, NbO) have attracted much attentions since the current nonvolatile memory (NVM) has been approaching the scaling limit. Meanwhile, selector devices are essential to address the sneak path issue which causes reading errors and hinders the implementation of RRAM in high-density cross-bar array architecture [3-4]. However, additional selector devices, e.g. a commonly proposed one selector-one resistor (1S-1R) design, increases the process complexity and cost. In this work, selectorless 1R RRAM devices have been demonstrated by utilizing the nonlinear (NL) resistive switching (RS) characteristics. Pulse operation voltage variation tolerance on SiOx-based stacking structures has also been characterized. The starting substrates are heavily-doped N+ Si wafers, and titanium nitride of 200 nm thickness was deposited on N+ Si substrate as bottom electrode. Then, 9 nm of SiOx and 4 nm of HfOx were deposited as RS dielectric layers for bilayer (HfOx/SiOx) structures by RF sputtering method. Pt (165nm) was deposited as top electrodes for RRAM devices (Fig. 1). Fig. 2 shows bipolar RS I-V characteristics during DC voltage sweeps for single-layer HfOx and bilayer devices. Both SET and RESET voltages are lower in single-layer HfOx devices than in bilayer devices possibly due to higher oxygen concentration. The SET voltage of single-layer HfOx devices is about 0.2 V lower than of single-layer SiOx devices, and RESET voltage is reduced to half (~ 0.5 V) with inserting a HfOx stack layer, which is potentially beneficial for low voltage operating applications. Also, the RESET current is critical for overall switching power in RRAM applications, is ~1 mA and has been found to be independent of the thickness ratio of stacks. Comparing the bilayer structure to the single-layer HfOxstructure, the current at -0.2 V is reduced from ~10-4 to ~10-6 A. It depicts that there was significantly increased resistance at low voltage region, which is proposed as a solution for sneak path issue in crossbar array applications. Nonlinearity (NL) is defined as the ratio of the current at full read voltage (i.e. -0.6 V) to the current at 1/3 read voltage (-0.2 V). The higher nonlinearity, the better ability is to avoid the sneak current interference. The NL characteristics in ILRS of all the devices are showed in Fig. 3. With a thin SiOx layer (2 nm) on the bottom of HfOx (11 nm) layer, the NL is ~3x in comparison to the single-layer HfOx layer devices. Based on our results, the bilayer RRAM device has been found to show the highest NL among the SiOx-based stacking structures. This makes SiOx-based bilayer devices a potential candidate for 1R selectorless RRAMs. To evaluate the voltage variation tolerance in pulse operation, the reset stop voltage effect has been studied. The RS I-V was characterized with increasing RESET stop voltage from -1.4 to -2.6 V for the bilayer and trilayer devices (Fig. 4). For bilayer devices, the high resistance state (HRS) resistance and memory window increase with increasing RESET stop voltage (Fig. 5). The bilayer devices with higher SET/RESET voltage variation tolerance (less variation below stop voltage of 2.2 V) and have been found to exhibit better NL characteristics (~10) than the trilayer devices, which shows larger switching voltage variation with changing reset stop voltage (Fig.6). In this study, build-in nonlinear characteristics have been realized for the SiOx-based one-resistor (1R) device without an additional diode or a selector. The highly nonlinear characteristics observed in SiOx-based bilayer devices are desirable in avoiding the read error and preventing sneak-path currents in crossbar arrays. Our results show that SiOx-based bilayer devices are promising for high-density, low-power, selectorless RRAM applications. Figure 1

Here we demonstrate low-power resistive switching in a Ni/SiNy/SiNx/p++-Si device by proposing a double-layered structure (SiNy/SiNx), where the two SiN layers have different trap densities. The LRS was measured to be as low as 1 nA at a voltage of 1 V, because the SiNx layer maintains insulating properties for the LRS. The single-layered device suffers from uncontrollability of the conducting path, accompanied by the inherent randomness of switching parameters, weak immunity to breakdown during the reset process, and a high operating current. On the other hand, for a double-layered device, the effective conducting path in each layer, which can determine the operating current, can be well controlled by the ICC during the initial forming and set processes. A one-step forming and progressive reset process is observed for a low-power mode, which differs from the high-power switching mode that shows a two-step forming and reset process. Moreover, nonlinear behavior in the LRS, whose origin can be attributed to the P-F conduction and F-N tunneling driven by abundant traps in the silicon-rich SiNx layer, would be beneficial for next-generation nonvolatile memory applications by using a conventional passive SiNx layer as an active dielectric.

This study proposes a method for a HfO2-based device to exhibit both resistive switching (RS) characteristics as resistive random access memory (RRAM) and selector characteristics by introducing vanadium (V) as the top electrode. This simple V/HfO2/TiN structure can demonstrate these two different properties depending on forming polarities. The RS mechanism is activated by a positive forming bias. In contrast, the selector property is induced by a negative forming bias. The material analyses firstly confirm the existence of V in the top electrode. Then the electrical measurements for the same V/HfO2/TiN structures but with different forming polarities were carried out to further investigate their DC sweeping characteristics to act as either a selector or RRAM device. Furthermore, reliability tests for both selector and RRAM devices were also conducted to confirm their switching stabilities. Finally, current fitting methods and temperature influence experiments were performed to investigate the carrier transport mechanisms. Finally, physical models were proposed to illustrate the selector property and RS mechanism for selector and RRAM devices, respectively. This simple device structure with its easy operating method accomplishes a significant advancement of devices combining both selector properties and RRAM for remarkable real applications in the near future.

Characteristics of HfOx-based resistive switching memory (RRAM) in Al/HfOx/Al and Al/AlOx/HfOx/Al structures were studied using a dynamic conductance method. Step-like RESET behaviors as well as pre- and post-RESET regions of operation were characterized. The results indicated that defects at the oxide interface caused cycling issues in the Al/AlOx/HfOx/Al structure. No such RESET behavior was observed for the Al/HfOx/Al structure. Current induced over-heating, which caused an early RESET event, could be avoided using current-sweep technique that caused less electrical and thermal stress in localized regions. The experimental results not only provided insights into potential reliability issues and power management in HfOx-based RRAM, but also helped clarifying the resistive switching mechanisms.

In this work, we present silicon process compatible, stable and reliable (>108 cycles), high non-linearity ratio at a half-read voltage (>5 × 105), high speed (

Oxide based resistive switching memory are the promising candidates for future non-volatile memory according to fast programing, low power operation, scalability and compatibility to the current CMOS process. Among, SiOx single layer resistive switching devices have been widely studied and characterized. The SiOx single layer resistive memory has good compatibility to CMOS fabrication process. However, it can only be programmed under the vacuum or non-oxidized ambient. Also, the previous results reported on SiOx-based memristors indicate that the electroforming and programming voltage is relatively higher than the other dielectric materials and obstructed for low-power applications. In this work, by using SiOx/HfOx stacking engineering, we have developed a low-voltage operation (< 2V) for SiOx-based ReRAM. The results show that with HfOx (3nm) on bottom, the metal-insulator-semiconductor (MIS) structures exhibit resistive switching at low voltage (x-based MIS devices which exhibit bipolar-type resistive switching behaviors with small memory window.Clearly, SiOx/HfOx stacking optimization not only maintains the RS behaviors even in air environment without any programming window degradation, but also further reduces the switching voltage below 2V. Figure 1 shows the results of three different structures, including SiOx single layer memristor, SiOx/HfOx bilayer memristor and HfOx single layer memristor. In terms of operation environment condition, inserting the HfOx layer would help the SiOx memristor to be able to programmed either under a pressure of 1E-4 torr or in the atmosphere. The HfOx single layer memristor has the lowest electroforming voltage of 2.3 V, and which in SiOx/HfOx stacks has been reduced significantly to 5 V comparing which of 14 V for SiOx single layer. For the SiOx/HfOx bilayer, a memory window of 4 decades is achieved and comparable to that of SiOx single layer, and larger than that of single layer HfOx by 2 decades. In terms of operation voltage, the set voltage is reduced from 4V to 2 V and the reset voltage is also suppressed significantly from 10 V to 0.3 V by inserting the 3 nm HfOx layer. Figure 2 shows the TEM images of both SiOx single layer memristor and SiOx/HfOx bilayer memristor. The 3 nm HfOx was deposited on N+ Si wafer at 250 oC by atomic layer deposition followed by 30 nm SiO2 deposition using e-beam evaporator and 160 nm TaN depositing by sputtering. Figure 3. The single layer HfOx-based MIS devices resistive switching behaviors. (a) The electroforming process, resistive switching behaviors in 20 times cycling. (b) The switching voltage (SET/RESET) and states (HRS/LRS) distribution. Figure 1

In this research, we investigated the conduction mechanism in metal-insulator transition (MIT) materials. Among these MIT materials (NbOx, NiOx, VOx, and TaS2), vanadium oxide–based selectors have been widely investigated because of their high switching speed (~10-ns transition time), sufficient non-linearity (>103), and endurance stability (~1010). Abnormal temperature-dependent degradation in the high resistive state was observed, as was studied in detail by a current fitting analysis and explored theoretically by electric (E-MIT) and thermal (T-MIT) modeling. The results suggest the existence of a MIT region located between the electrode and the localized filament. To improve the localized transition efficiency, we propose an enhanced-type MIT architecture to bypass the E-MIT and T-MIT universal rule with the novel structure of vanadium top electrode device. As compared with a vanadium oxide middle-layer device, the electrical transition efficiency is improved 2-fold as evidenced by thermal cycling material analysis, as well as boosting endurance reliability to 107 at 65 °C. Finally, for the first time, a potential neuromorphic computing application featuring a damping oscillator has been demonstrated in this enhanced-type MIT architecture, with a high damping ratio with 10-fold smaller area and 5-fold smaller energy than complementary metal–oxide–semiconductor (CMOS) devices. This presents a promising milestone for ultralow power neuromorphic system design and solutions in the near future.

In this work, SiCxNy-based resistive switching memory by using a single precursor for the back end of line (BEOL) integration has been investigated. SiCxNy films were deposited on the aluminum (Al) substrates using plasma enhanced atomic layer deposition (PEALD) method. The effects of SiCxNy chemical structure with respect to resistive switching characteristics have been studied, and the results suggest that the resistive switching mechanism is dominated by the interfacial Schottky junction with SiCxNy composition. This work not only demonstrates a PEALD method in fabricating SiCxNy-based electronics active devices but also provides additional insights into the interaction between the electrical and chemical structures in bi-functional resistive switching or threshold switching behavior. A demonstrated PEALD tool with simple single-precursor for SiCxNy deposition shows excellent feasibility to be used as functional memory and selector devices, further giving the potential pathway for advanced BEOL process integration.

This letter presents dual functions including selector and memory switching in a V/SiO x /AlO y /p++Si resistive memory device by simply controlling compliance current limit (CCL). Unidirectional threshold switching is observed after a positive forming with low CCL of 1 μA. The shifts to the V-electrode side of the oxygen form the VO x layer, where the threshold switching can be explained by the metal-insulation-transition phenomenon. For higher CCL (30 μA) applied to the device, a bipolar memory switching is obtained, which is attributed to formation and rupture of the conducting filament in SiO y layer. 1.5-nm-thick AlO y layer with high thermal conductivity plays an important role in lowering the off-current for memory and threshold switching. Through the temperature dependence, high-energy barrier (0.463 eV) in the LRS is confirmed, which can cause nonlinearity in a low-resistance state. The smaller the CCL, the higher the nonlinearity, which provides a larger array size in the cross-point array. The coexistence of memory and threshold switching in accordance with the CCL provides the flexibility to control the device for its intended use.

Resistive random access memory (RRAM) using various metal oxides (i.e., SiO 2 [1], HfO 2 , NiO[2], Al 2 O 3 , NbO) have attracted a great deal of attention since the current nonvolatile memory (NVM) has been approaching the scaling limits. Meanwhile, the undesired sneak current through neighboring unselected cells deteriorates the read margin and limits the maximum size of a crossbar array (i.e. read margin $\sim$ 10%) [3]–[4]. And the selector devices have been used to resolve the sneak path current issue. However, the additional selector device in the so-called 1S-1R architecture (i.e. one selector-one resistor -Fig. 1 (a)) increases the cell size, process complexity, and cost. In this work, a nonlinear (NL) resistive switching (RS) in a multilevel lR-only selectorless RRAM cell has been demonstrated by using a graphite-based stacked RRAM device.

In this work, we fabricated HfO x -based RRAM-type memristors that are CMOS-compatible and analyzed its synapse characteristics. Ni/HfO x /p++Si filament-type device exhibits abrupt resistive changes in both SET and RESET operations in the same pulse response as the DC sweep, while interface-type Ni/HfO x /n++Si devices show gradual changes. Interface-type devices exhibit more dynamic states as the temperature rises, while the recognition rate of neural network using memristive synapses did not degrade for T < 145 °C. Our results suggest that neuromorphic chips fabricated using RRAM-type memristors can operate under wide temperature range.

In this work, we investigated SiO(x)-based interfacial resistive switching in planar metal-insulator-metal structures using physical/chemical/electrical analyses. This work helps clarify the interfacial reaction process and mechanism in SiO(x), and also shows the potential for high temperature operation in future nonvolatile memory applications.

For the first time, a comprehensive study of Vanadium oxide-based selector characteristics with a universal model observed by thermal and electrical induced threshold switching (TS) phenomena at interface is presented in this work. The model can explain that the resistance evolution by thermal temperature in TS behaviors, as well as the resistance gradually increases with cycling (“seasoning effect”). Compatible current density (107∼109 A/cm2) and selectivity (∼100) with physical understanding of evolution in energy barrier and MIT metallic state modulation are studied. The results show a promising design guideline for future storage-class memory (SCM) applications.

We observe how temperature and compliance currents (CCs) affect the coexistence of nonvolatile resistive memory switching (NVMS) and volatile threshold switching (VTS) in a complementary metal-oxide-semiconductor compatible Cu/SiOx/p++-Si device. NVMS and VTS behaviors are investigated at different temperatures (300 K, 360 K, and 420 K) and different CCs (100 nA–1 mA). In CCs smaller than 1 mA, NVMS and VTS coexist, and as the CC decreases, the frequency of occurrence of VTS tends to increase. The frequency of VTS events increases at higher temperatures. We demonstrate the transient characteristics of the device using a pulse transient for SET, RESET, and volatile switching. These results could be used to artificially mimic the long-term and short-term plasticity of biological synapses using the phenomena of NVMS and VTS.We observe how temperature and compliance currents (CCs) affect the coexistence of nonvolatile resistive memory switching (NVMS) and volatile threshold switching (VTS) in a complementary metal-oxide-semiconductor compatible Cu/SiOx/p++-Si device. NVMS and VTS behaviors are investigated at different temperatures (300 K, 360 K, and 420 K) and different CCs (100 nA–1 mA). In CCs smaller than 1 mA, NVMS and VTS coexist, and as the CC decreases, the frequency of occurrence of VTS tends to increase. The frequency of VTS events increases at higher temperatures. We demonstrate the transient characteristics of the device using a pulse transient for SET, RESET, and volatile switching. These results could be used to artificially mimic the long-term and short-term plasticity of biological synapses using the phenomena of NVMS and VTS.

In this work, the nonlinear (NL) characteristics of bi-layer high-k/low-k dielectrics structure, i.e. high-k layer with the low-k layer, are for selectorless oxide-based resistive random-access memories (RRAM) memory array application. It has been shown that such structure enhances the read currents at full read voltage (∼10-3 A) as compared to the bi-layer low-k/low-k structure (∼10-4 A), reduces low-voltage current, increases I-V nonlinearity and thereby suppresses the sneak path currents in the selectorless RRAM. Improved seasoning effect has also been demonstrated using the bilayer dielectric structure. The Fowler-Nordheim tunneling behavior has been found in the first RESET process (-0.45 to -1.25 V) as followed by the high self-rectifying characteristics that enlarge the immunity to the sneak path current and reduce the read errors in the array applications. The breakdown controllability of the forming process dominates the followed seasoning cycles which leads to two different performances in bilayer stacks i.e. efficient seasoning and inefficient seasoning, which provides an intrinsic design of selectorless RRAM devices. The device characteristics with current transport mechanisms have also been investigated. Our results provide additional insights into ways to achieve high performance and excellent reliability of built-in nonlinearity in selectorless RRAM (NL > 120, memory window > 100, sub-μs switching speed, and NL retention) for the future low-power RRAM memory array configurations.

We report on a highly compact, one diode-one resistor (1D-1R) nanopillar device architecture for SiOx-based ReRAM fabricated using nanosphere lithography (NSL). The intrinsic SiOx-based resistive switching element and Si diode are self-aligned on an epitaxial silicon wafer using NSL and a deep-Si-etch process without conventional photolithography. AC-pulse response in 50 ns regime, multibit operation, and good reliability are demonstrated. The NSL process provides a fast and economical approach to large-scale patterning of high-density 1D-1R ReRAM with good potential for use in future applications.

Recently, resistive random access memory (RRAM) using various metal oxides (i.e., SiO 2 [1], HfO 2 , NiO[2], Al 2 O 3 , NbO) have attracted a lot of attentions since the current nonvolatile memory (NVM) approaching the scaling limits. Meanwhile, the selector devices are essential to address the sneak path issue which causing the reading errors in high-packing-density cross-bar RRAM array. Several types of selector devices with threshold switching (TS) behavior has been investigated, such as rectifying diode[3], varistors[4], ovonic TS (OTS)[5], metal-insulator transition (MIT)[6] etc. In this work, the characteristics of electrically driven MIT (E-MIT) in both Nb-doped SrTiO 3 and HfO 2 -based selector devices has been investigated.

Intrinsic unipolar SiOx-based resistance random access memories (ReRAM) characterization, switching mechanisms, and applications have been investigated. Device structures, material compositions, and electrical characteristics are identified that enable ReRAM cells with high ON/OFF ratio, low static power consumption, low switching power, and high readout-margin using complementary metal-oxide semiconductor transistor (CMOS)–compatible SiOx-based materials. These ideas are combined with the use of horizontal and vertical device structure designs, composition optimization, electrical control, and external factors to help understand resistive switching (RS) mechanisms. Measured temperature effects, pulse response, and carrier transport behaviors lead to compact models of RS mechanisms and energy band diagrams in order to aid the development of computer-aided design for ultralarge-v scale integration. This chapter presents a comprehensive investigation of SiOx-based RS characteristics and mechanisms for the post-CMOS device era.

We realize a device with biological synaptic behaviors by integrating silicon oxide (SiOx) resistive switching memory with Si diodes to further minimize total synaptic power consumption due to sneak-path currents and demonstrate the capability for spike-induced synaptic behaviors, representing critical milestones for the use of SiO2-based materials in future neuromorphic computing applications. Biological synaptic behaviors such as long-term potentiation, long-term depression, and spike-timing dependent plasticity are demonstrated systemically with comprehensive investigation of spike waveform analyses and represent a potential application for SiOx-based resistive switching materials. The resistive switching SET transition is modeled as hydrogen (proton) release from the (SiH)2 defect to generate the hydrogenbridge defect, and the RESET transition is modeled as an electrochemical reaction (proton capture) that re-forms (SiH)2. The experimental results suggest a simple, robust approach to realize programmable neuromorphic chips compatible with largescale complementary metal-oxide semiconductor manufacturing technology.

Intrinsic unipolar SiOx-based Resistive-RAM (ReRAM) characteristics have been investigated. The cross-bar MIM structures have been examined under AC frequency response, by varying device area, temperature and current states. The results provide additional insights into the hopping/switching mechanisms. For the first time, by using SiOx/HfOx stacking engineering, we have developed a low-voltage operation (< 2V) for SiOx-based ReRAM. The SiOx/HfOx stacking optimization not only maintains the RS behaviors even in air environment without any programming window degradation, but also further reduces the switching voltage below 2V.

In this work, the simultaneous detection of threshold switching and bipolar memory switching in Ag/SiNx/p++-Si devices is investigated. In the DC sweep mode, threshold switching is observed with low compliance current limit (CCL) of 1 μA while memory switching is dominant when high CCL (1 mA) is applied. It is found that in the pulse switching mode, pulse amplitude is an important factor in determining the nature of switching. It has been proven that the strength of the Ag filament formed in the SiNx determines the nonvolatile property of the switching. The undirectional threshold switching behavior in low currents of Ag/SiNx/p++-Si devices could be used as a selector for a low-power unipolar memory. Moreover, operating in two modes in one device will provide more flexibility in device design.

A feasible approach is reported to reduce the switching current and increase the nonlinearity in a complementary metal-oxide-semiconductor (CMOS)-compatible Ti/SiNx /p+ -Si memristor by simply reducing the cell size down to sub-100 nm. Even though the switching voltages gradually increase with decreasing device size, the reset current is reduced because of the reduced current overshoot effect. The scaled devices (sub-100 nm) exhibit gradual reset switching driven by the electric field, whereas that of the large devices (≥1 µm) is driven by Joule heating. For the scaled cell (60 nm), the current levels are tunable by adjusting the reset stop voltage for multilevel cells. It is revealed that the nonlinearity in the low-resistance state is attributed to Fowler-Nordheim tunneling dominating in the high-voltage regime (≥1 V) for the scaled cells. The experimental findings demonstrate that the scaled metal-nitride-silicon memristor device paves the way to realize CMOS-compatible high-density crosspoint array applications.

We realize a device with biological synaptic behaviors by integrating silicon oxide (SiOx) resistive switching memory with Si diodes. Minimal synaptic power consumption due to sneak-path current is achieved and the capability for spike-induced synaptic behaviors is demonstrated, representing critical milestones for the use of SiO2–based materials in future neuromorphic computing applications. Biological synaptic behaviors such as long-term potentiation (LTP), long-term depression (LTD) and spike-timing dependent plasticity (STDP) are demonstrated systematically using a comprehensive analysis of spike-induced waveforms and represent interesting potential applications for SiOx-based resistive switching materials. The resistive switching SET transition is modeled as hydrogen (proton) release from (SiH)2 to generate the hydrogen bridge defect and the RESET transition is modeled as an electrochemical reaction (proton capture) that re-forms (SiH)2. The experimental results suggest a simple, robust approach to realize programmable neuromorphic chips compatible with large-scale CMOS manufacturing technology.

Sneak path current is a severe hindrance for the application of high-density resistive random-access memory (RRAM) array designs. In this work, we demonstrate nonlinear (NL) resistive switching characteristics of a HfO x /SiO x -based stacking structure as a realization for selector-less RRAM devices. The NL characteristic was obtained and designed by optimizing the internal filament location with a low effective dielectric constant in the HfO x /SiO x structure. The stacking HfO x /SiO x -based RRAM device as the one-resistor-only memory cell is applicable without needing an additional selector device to solve the sneak path issue with a switching voltage of ~1 V, which is desirable for low-power operating in built-in nonlinearity crossbar array configurations.

Resistive random access memories (ReRAM) has attracted tremendous attention as a promising candidate for non-volatile memory. ReRAM can be classified into two categories: unipolar and bipolar memory. The advantage of unipolar memory is that it can be integrated into simple 1D-1R architecture with low static power consumption and constrained sneak-path issue. This is because unipolar memory does not require opposite voltage polarities for on/off switching [1]. SiO x has long been used as gate dielectrics for MOSFET and recently proved to be an active unipolar ReRAM material [2, 3]. Here we report SiO x -based 1D-1R high density nanopillar ReRAM via nanosphere lithography.

We demonstrate key factors enabling mobility improvement at both low charge density and high density (>5×1012/cm2) in In 0.7 Ga 0.3 As quantum-well MOSFETs. We further show sub-threshold swing (SS) and on-current (I d ) improvement in tunneling FETs (TFETs). By reducing EOT, optimizing the top-barrier/high-к interface, and confining carriers in In 0.7 Ga 0.3 As channel using In 0.52 Al 0.48 As bottom-barrier, SS and mobility of MOSFETs were improved from 152 to 99 mV/dec and from ∼2500 to ∼5000 cm2/V-s, respectively. TFETs achieved small SS (96 mV/dec) and high I d (55 µA/µm) due to low EOT and abrupt, vertical insitu grown III–V epitaxial junctions.

This work compares device performance for In 0.53 Ga 0.47 As M OSFETs using single HfO 2 gate dielectric with stacked gate dielectrics using various interfacial layers between HfO 2 and In 0.53 Ga 0.47 As substrate including Al 2 O 3 , HfAlO x , LaAlO x , and LaHfO x . Of the gate stacks studied, Al 2 O 3 /HfO 2 , HfAlO x /HfO 2 , and LaAlO x /HfO 2 bilayer gate dielectrics exhibit lower subthreshold swing, higher drive current and transconductance compared to single HfO 2 with similar equivalent oxide thickness (EOT) of about 10A. This is believed t o be due to better interface quality between interfacial dielectrics and substrate, and confirmed by frequency dispersion and interface state density measurements.

Self-compliance characteristics and reliability optimization are investigated in intrinsic unipolar silicon oxide (SiOx)-based resistive switching (RS) memory using TiW/SiOx/TiW device structures. The program window (difference between SET voltage and RESET voltage) is dependent on external series resistance, demonstrating that the SET process is due to a voltage-triggered mechanism. The program window has been optimized for program/erase disturbance immunity and reliability for circuit-level applications. The SET and RESET transitions have also been characterized using a dynamic conductivity method, which distinguishes the self-compliance behavior due to an internal series resistance effect (filament) in SiOx-based RS memory. By using a conceptual “filament/resistive gap (GAP)” model of the conductive filament and a proton exchange model with appropriate assumptions, the internal filament resistance and GAP resistance can be estimated for high- and low-resistance states (HRS and LRS), and are found to be independent of external series resistance. Our experimental results not only provide insights into potential reliability issues but also help to clarify the switching mechanisms and device operating characteristics of SiOx-based RS memory.

The physical mechanisms of unipolar resistive switching (RS) in SiOx-based resistive memory are investigated using TaN/SiOx/n++Si and TiW/SiOx/TiW device structures. RS is independent of SiOx thickness and device area, confirming that RS occurs in a localized region along a filamentary pathway. Results from experiments varying electrode type, series resistance, and the oxygen content of SiOxNy materials show the potential to optimize switching performance and control device programming window. Device materials with stoichiometry near that of SiO2 are found to have better operating stability as compared to extrinsic, N-doped SiOxNy materials. The results provide further insight into the physical mechanisms of unipolar operation and lead to a localized switching model based on electrochemical transitions involving common SiOx defects. High-temperature data retention measurements for over 104 s in high- and low-resistance states demonstrate the potential for use of intrinsic SiOx RS devices in future nonvolatile memory applications.

Deep-submicron In 0.7 Ga 0.3 As buried-channel MOSFETs with various gate lengths down to 40 nm are demonstrated. In 0.7 Ga 0.3 As buried-channel MOSFETs were fabricated on an epitaxial wafer using an InP/In 0.52 Al 0.48 As double barrier. The device characteristics were analysed, including subthreshold swing, transconductance and drive current. Good scaling behaviour was observed for these III-V MOSFETs. For a 40-nm gate length device, the VT roll-off is around 100 mV, the subthreshold swing is 132 mV/dec and DIBL is 214 mV/V.