Search

We describe a controllable sliding method for fabricating millions of isolated femto- to nanoliter-sized droplets with defined volume, geometry and position and a speed of up to 375 kHz. In this work, without using a superhydrophobic or superoleophobic surface, arrays of droplets are instantly formed on the patterned substrate by sliding a strip of liquid, including water, low-surface-tension organic solvents and solution, along the substrate. To precisely control the volume of the droplets, we systemically investigate the effects of the size of the wettable pattern, the viscosity of the liquid and sliding speed, which were found to vary independently to tune the height and volume of the droplets. Through this method, we successfully fabricated an oriented single metal–organic framework crystal array with control over their XY positioning on the surface, as characterized by microscopy and X-ray diffraction (XRD) techniques.

We have proposed two algorithms to demonstrate the relationship between W oxidation time and switching speed in this paper. The demonstration is carried out on a 128Kb test macro of AlOx/WOx bi-layer RRAM which was fabricated with 0.18µm standard logic process. Increasing the W oxidation time properly could achieve a faster switching speed while the overmuch oxidation time will result in performance decreasing. In addition to the switching speed, the oxidation time has no obvious effect on Ron and forming success rate. The typical Roff/Ron resistive window is about 1000× in our work.

In this work, the advances in the resistance switching characteristics of stoichiometric ZrO 2 thin films were studied. The Al/ZrO 2 /Al structure exhibits reliable and reproducible switching behaviours. The thickness dependence and electrode size effect was demonstrated and understood in terms of a combined model of conductive filament/carriers trapping. Analyses of current–voltage characteristics were performed and it is suggested that the resistive switching characteristics of the ZrO 2 film are governed by both the electrode/interface effect and the formation of conductive multi-filaments.

The multi-bit storage realization based on chalcogenide thin film transistor is put forward first here, in which the chalcogenide film acts as not only phase change material but also semiconductor layer. The channel length of thin film transistor was modified by reversible phase change between amorphous and crystalline of chalcogenide thin film adjacent to source and drain. Consequently different read-out current can be achieved to realize multi-bit storage in one single cell.

We found CuOx thin film with gradual oxygen concentration (GOC) distribution enhances resistive switching characteristics for nonvolatile memory applications. Using Al/ GOC CuOx /Cu structure, not only no forming is needed, also the endurance of switching is greatly enhanced. The device with GOC CuOx demonstrates resistance on/off ratio greater than 100, and endurance of more than 12000 cycles. A ramped pulses series (RPS) operation method is also put forward, which can improve switching stability and cycling endurance remarkably. A method for minimizing the dispersion of Vreset by optimizing amplitude of pulse is proposed further. Dispersion of Vreset can be minimized by using optimized Vstart of RPS. And this phenomenon agrees well with the Joule heating model that the RESET process of memory switching is associated with rupturing of filaments by Joule heating.

A method has been introduced to realize multi-states storage in phase change memory (PCM) by using stacked phase change films with different amorphous resistivity. The amorphous resistivity of each phase change layer was selected to make the stacked films crystallize successively with the increase of current, and so obtain four resistance states. The thickness of each phase change layer was also optimized to ensure enough resistance difference between neighboring storage state. The thermal conduction simulation was performed, and the results indicate that the stacked Si–Sb–Te films with suitable composition, resistivity and thickness in each layer can crystallize successively with the increase of current and realize multi-states storage in PCM. A memory cell with stacked film structure (Si16Sb33Te51/Si4Sb46Te50/Si11Sb39Te50) was prepared. The film thicknesses of Si16Sb33Te51, Si4Sb46Te50 and Si11Sb39Te50 were optimized to be 40, 80, and 20 nm, respectively. The current–voltage (I–V) characteristics and the resistance–current (R–I) characteristics were measured. The results confirmed the four-state storage capability of the memory cell with this stacked film structure.

The characteristics of phase change memory devices in size of several micrometers and with pure Ge2Sb2Te5 (GST), N-doped GST, and Si-doped GST films were investigated and compared with each other. The Si-doped GST device can perform SET and RESET cycles, even if the Si dopant is as small as 4.1 at. %. But the GST and N-doped GST device cannot perform the RESET process, though the SET state resistance of N-doped device is almost the same as that of Si-doped device and larger than that of GST device. In order to explain this phenomenon, the electrical and DSC characteristics of three kinds of films were investigated. Phase separation was found in Si-doped GST films. The reason of the RESET ability of Si-doped GST devices is supposed to be the existence of rich Si phases which act as micro-heaters. Thermal conduction simulations confirmed this supposition and indicate that the separated high resistance phase (rich Si phase) can heat the active volume of device efficiently and reduce the writing current largely.

The switching characteristics of the electrical phase-change memory device using a SiSbTe film were studied. The SiSbTe film has a wider variation of electrical resistivity (up to 107 times) along with crystallization than that of the conventionally used Ge2Sb2Te5 film, and the SiSbTe film crystallizes predominantly into the hexagonal phase in a manner similar to the Sb2Te3 phase. The threshold voltage of the device is 5.87 V. The device was successfully operated with a 100 ns–5.5 V pulse for setting and a 20 ns–3 V pulse for resetting. The RESET current is about 1.37 mA, and the programming energies for resetting and setting are about 110 pJ and 60 pJ, respectively. More than 100 cycles were achieved with a RESET/SET resistance ratio higher than 50. In addition, multiple stable resistance stages can be obtained by adjusting the SET pulse, which makes multibit storage per cell possible.

The performance of Nonvolatile phase-change-memory material Ge2Sb2Te5 and nitrogen doped Ge2Sb2Te5 as well as its device cell was investigated. The effects of the annealing temperature on the resistivity and crystal structure of the Ge2Sb2Te5 were studied. The Hall measurement shows the hole mobility decreased with the changing of film thickness from 10 nm. to 100 nm The GST resistivity can be increased effectively by doping nitrogen and the decrease of the film thickness. The high resistive GST is indispensable to minimize threshold voltage of PCRAM.

With the increasing requirement of high density memory technology, a new cell structure—1TR has received much attention. It consists of a single thin film transistor (TFT) with chalcogenide Ge2Sb2Te5 as the channel material. In order to evaluate the feasibility of its application in the field of non-volatile memory, we take a further step in researching on the characteristics of GST-TFT. We fabricated a back-gate GST-TFT and investigated the output and transfer characteristics of its two states. The experimental results show that gate voltage can modulate the GST channel currents in both the amorphous and the crystalline states. Based on the experiments, we can expect that this novel device can ultimately lead to a new nonvolatile memory technology with even higher storage density.

Electrical properties and crystallization behaviour of Si–Sb–Te films were studied and compared with those of a Ge2Sb2Te5 film. The resistivity ratio of Si–Sb–Te films can reach 106 during the amorphous–crystalline transition, accompanied with a small thickness change (less than 3%). The melting temperature of Si–Sb–Te films is lower than that of a Ge2Sb2Te5 film. Furthermore, the switching characteristics of the device using a Si10.7Sb39.5Te49.8 film were also studied. The device can be successfully switched with a 4 V, 100 ns pulse for SET operation and a 5 V, 40 ns pulse for RESET operation. A small RESET current and low power consumption can be obtained, which may be attributed to the low melting temperature and the high crystalline resistivity of Si–Sb–Te films. These results indicate the feasibility of Si–Sb–Te films in the application of phase-change random access memory.

A nano-scale-sized 3D phase change memory element has been successfully fabricated using novel metal sidewall pattern technology, based entirely on a CMOS process which is independent of lithographic size limitations. With Ge2Sb2Te5 (GST) as the phase change material, a 280 nm × 35 nm contact area cell (equal to 100 nm contact diameter) has been successfully fabricated by 5 µm university lithographic techniques. The effects of annealing temperature on the GST resistivity and crystal structure have been studied. Static mode switching (dc tests) and pulse mode tests were performed, and an on/off ratio greater than 100 has been achieved.

The multi-state storage capability of phase-change memory (PCM) was confirmed by using stacked chalcogenide layers as storage medium. The stacked films were prepared by stacking a pure Ge2Sb2Te5 (GST) layer, a tungsten layer and a silicon-doped GST layer. The electrical properties of the stacked films were also investigated. The results show that there are two negative differential resistance areas in the current-voltage (I–V) curve and three steps with three relatively stable resistance values in the resistance-voltage (R–V) curve, which indicate that the multi-state storage of PCM can be realized by using this stacked film structure. Qualitative analysis reveals that the multi-state storage capability of this stacked film structure is due to the successive crystallizations in a silicon-doped GST layer and a pure GST layer.

A Phase Change Access Memory (PRAM) cell with stacked phase-change layers and heater layers is prepared. Multi-bit storage in the reset process of the PRAM is realized by this stacked structure including phase-change layers with uniform thickness and heater layers with different thickness. The thermal simulation results show three phase-change layers in three temperature zones, and they will transform from polycrystalline to amorphous state layer by layer. There are four levels of resistance appearing in the R –V characteristics, and 2-bit storage is realized. (© 2007 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Impacts of annealing temperature and film thickness to the resistivity of Ge 2 Sb 2 Te 5 (GST) have been studied. The resistivity of GST drops when the annealing temperature reaches 180 °C, rises above 360 °C and the thicker film crystallized more easily. Electronic device of phase change memory also has been fabricated with metal sidewall technology using 5 μm lithographic technology. The device was successfully programmed by 100 ns of 5 V pulse for SET and 10 ns of 10 V pulse for RESET. More than 100 times on/off ratio has been reached.

Process optimization strategy to reduce random threshold voltage (Vt) variation for CMOS at 65nm and beyond is presented. The impact of related process parameters such as halo/Vt implant species, energy and dosage on Vt mismatch are analyzed and compared by 3D TCAD simulation. It is revealed that the random dopant fluctuation (RDF) can be dramatically suppressed by carbon implant with sufficient dosage combines proper energy. Besides, Vt tuning and halo implants by indium is recommended because it is less susceptible to Vt variation than Bf2. All these results of process optimization can be well explained by the shift of impurity doping level near the surface.

A new Cu x Si y O resistive memory, which is different from Cu-doped SiO 2 or CuxO binary oxide, is integrated successfully in standard logic technology for the first time. Key breakthrough is that data retention (10 years@ 150°C), resistance distribution (with 50x window@125 °C ) and disturbance immunity significantly improved with integration simplicity advantage, as demonstrated on a 1Mb test chip. The activation energy of Cu vacancy migration in Cu x Si y O increases by 5 times than that in Cu x O, giving rise to the great performance improvement. The solution is promising for both high density and low cost embedded nonvolatile memory (NVM) applications.

A Cu x O-based resistive memory is successfully integrated in 0.13µm logic process. Operation algorithm is optimized to achieve low power consumption with reset current down to 30 µA. High thermal stability and small cell size less than 22F2 have been demonstrated. The advantages make this device promising for system on chip non-volatile memory applications.

The long retention, more than 10 years at 85degC, and excellent thermal reliability memory of TiN-Cu x O-Cu (with TiN cap layer as top electrode) is reported. TiN cap layer results in more stable reset from low resistance state (LRS) to high resistance state (HRS) under positive pulse and SET under negative pulse, which is beneficial for providing large programming current or voltage on the resistive random access memory (RRAM) resistor connected in series with a select transistor. Results show that the structure of TiN-Cu x O-Cu with its compatibility to CMOS technology appears a promising memory device for embedded application.

For the first time, we report that the copper oxide (CuxO) based resistive random access memory (RRAM) cell can achieve 104 cycles (i.e. ~10x better) as a new record as well as elimination of the initial ?forming? than reported in literature. The copper oxide is integrated in MIM (metal-insulator-metal) structure and is grown by plasma oxidation of Cu substrate, with CuO near upper surface and graded CuxO (i.e. increasingly Cu rich or O-vacancies rich) toward the Cu substrate. A thinner CuO upper layer can eliminate ?forming? process and, for in turn, greatly enhance the endurance of resistive switching by eliminating the damage during the ?forming? process.

Si-Sb-Te (SST) system materials were investigated for non-volatile phase change memory application. By contrast to the conventional GST films, the SST films exhibit stronger thermal stability and smaller RESET current, which were resulted from the self-confine and self-heat mechanisms by the amorphous Si-rich regions surrounding the phase change crystalline in SST. It shows a good promise for non-volatile memory applications.

The novel phase change materials Si-Sb-Te films were prepared. The crystallization temperature of films increases with the increasing of Si concentration. Phase separation was observed in the Si-Sb-Te films, the dominant phase is Sb2Te3. The melting temperature of Si-Sb-Te decreased to ~550°C lower than 640°C of Ge2Sb2Te5. The decrease of film thickness of Si-Sb-Te films is less than 2% after annealing at 400°C, which is less than ~7% of the film thickness change of Ge2Sb2Te5 film. The crystalline resistivity of Si-Sb-Te films increased and the ratio of amorphous/crystalline resistivity of Si-Sb-Te films increased also comparing with Ge2Sb2Te5 film, which is benefit to reduce the writing current and keep higher on/off ratio of phase change memory. Reversible switch was performed in the devices with Si-Sb-Te films. The device with Si14.3Sb28.6Te57.2 film can be programmed with a 100 ns SET pulse and a 20 ns RESET pulse. The Reset current is only 1.37mA for a 10μm-sized device.

A novel 2D nanometer edge contact type cell for phase change RAM is manufactured, in which the active area can be controlled mainly by the thickness of both bottom electrode film and the GST film. The high resistive GST is indispensable to minimize the writing current and threshold voltage of PCRAM. The GST resistivity can be increased effectively by doping nitrogen and the nitrogen-doped film is first used in the novel 2D nanometer structure successfully for reducing the threshold voltage application. It is found the phase change from FCC to hexagonal structure is suppressed by nitrogen doping, while 3 stable resistance states is first found in the resistivity-annealling temperature curve for the film by sputtering method, which might be used in multilevel PCRAM.

The effects of interface reaction, which were proved to affect the device performance significantly, were investigated in the AlO x /WO x bilayer resistive switching memory. The formation of the AlO x layer is due to the reaction of the Al top electrode with the oxygen in the WO x surface during the post-annealing process. It was observed that longer tungsten oxidation time can decrease the forming voltage and reset current. Transmission electron microscopy analysis showed that longer tungsten oxidation time leads to the formation of a thinner AlO x layer under the same post-annealing conditions. It was deduced that the different oxygen composition in the WO x surface may be the origin of the different AlO x layer thickness observed. The X-ray photoelectron spectroscopy results of the WO x surface indicated that the W6+/W5+ ratio decreased with increasing W oxidation time, which explained the different thickness of AlO x , thus resulting in different resistive switching characteristics. This study paved the way for the optimization of the process of fabricating AlO x /WO x bilayer resistive switching memory.

Bipolar and unipolar resistive switching was alternatively obtained in CuxSiyO resistive memory by controlling the voltage polarity and current compliance during the electroforming process. The dual switching modes showed significant differences in electrical parameters, such as switching voltage, gradual/sharp RESET, and ON/OFF resistance. Analyses of current–voltage (I–V) curve fitting and temperature coefficient relationship (TCR) indicated that the conductive filament was composed of vacancies in bipolar devices but metallic Cu in unipolar devices. A possible conduction model was sketched to interpret the coexistence of dual resistive switching.

Heterojunction diodes are fabricated using p-type Ge2Sb2Te5 and low doped n-type silicon wafer. Rectification is observed with a ratio of forward-to-reverse current as high as 104 and 103 for crystal-Ge2Sb2Te5/n-Si junction and amorphous-Ge2Sb2Te5/n-Si junction, respectively. The approximate equilibrium energy-band diagrams for both crystal-Ge2Sb2Te5/n-Si heterojunction diodes and amorphous-Ge2Sb2Te5/n-Si heterojunction diodes are proposed to explain the properties of the p-Ge2Sb2Te5/n-Si heterojunction diode. Properties of a p-n heterojunction diode based on Ge2Sb2Te5 are proposed to apply in 0T1R cross-point structure array for reliable read operation and for decreasing the sneaking current.

For the embedded application of the resistive switching memory using Cu x O films, the controllable switching polarity and optimized low resistance state was investigated. Stable bipolar switching behavior was demonstrated for the TaN / Cu x O / Cu device. TaON was observed at the anode interface by x-ray photoelectron spectroscopy and transmission electron microscopy, which is believed to play a key role in the resistance transition. The physics behind this phenomenon of reactive top-electrode is revealed. A filament/charges trapped combined model is proposed to clarify the electrical characteristics of the top-electrode/oxide reactions. This observation presents a unique opportunity to elucidate a universal mechanism for the resistive switching of transitional metal oxides.

The resistance switching characteristics of stoichiometric ZrO2 film were investigated for nonvolatile memory. The Al∕ZrO2∕Al device presents reliable and reproducible switching behaviors. The on/off ratio of two stable states is larger than 2×103. It is suggested that the current-voltage characteristics are governed by the Schottky conduction mechanism in high voltage region, while the filament conduction is suggested in low voltage region. The switching process is explained in terms of the spontaneous reversible reaction between electrode and ZrO2 films with the contribution of Joule heating effect by the external current. It provides a possible solution for low device yield of nonstoichiometric oxides.

The dynamic oscillation in the current-time characteristics of Ge 2 Sb 2 Te 5 and Sb-doped Ge 2 Sb 2 Te 5 thin-film materials was investigated using a scanning electrical nanoprobe. The dynamic oscillation was attributed to the threshold switching of the amorphousphase Ge 2 Sb 2 Te 5 and doped Ge 2 Sb 2 Te 5 thin films. The microscopic mechanism of the threshold switching behavior was also studied. X-ray diffraction showed that the excess Sb improved the crystallization of Ge 2 Sb 2 Te 5 during postannealing at 300°C. Sb-doping also increased the threshold switching speed.