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The concept of metamaterials emerged in years 2000 with the achievement of artificial structures enabling non conventional propagation of electromagnetic waves, such as negative phase velocity of negative refraction. The electromagnetic response of metamaterials is generally based on the presence of optically-resonant elements (or meta-atoms) of sub-wavelength size and well designed morphology so as to provide the desired electric and magnetic optical properties. Top-down technologies based on lithography techniques have been intensively used to fabricate a variety of efficient electric and magnetic resonators operating from microwave to visible light frequencies. However, the technological limits of the top-down approach are reached in visible light where a huge number of nanometre sized elements is required. We show here that the bottom-up fabrication route based on the combination of nanochemistry and of the self-assembly methods of colloidal physics provide an excellent alternative for the large scale synthesis of complex meta-atoms, as well as for the fabrication of 2D and 3D samples exhibiting meta-properties in visible light., Comment: 8 pages, 7 figures

Using data retention circuits that include crystalline oxide semiconductor transistors as backup circuits for power gating, a processor system can reduce standby leakage current significantly. This is effective in the Internet of Things (IoT) applications that require standby power reduction. The crystalline oxide semiconductor transistor can constitute a nonvolatile data retention circuit easily because it exhibits significantly lower off-state current than a silicon transistor and is highly compatible with a CMOS logic circuit. The backup circuit can achieve 2-clock-cycle data backup and 4-clock-cycle data restore; thus, the processor system can efficiently perform temporally fine-grained power gating and can achieve longer standby times. Furthermore, area overheads due to the backup circuits are kept very small because the crystalline oxide semiconductor transistors are stacked on silicon transistors.

In this letter, we report the electrical characteristics of a crystalline oxide semiconductor, especially $\boldsymbol {c}$ -axis aligned crystalline In–Ga–Zn–O (CAAC-IGZO) field-effect transistors (FETs) having a surrounded-channel structure with 51-nm channel lengths, 11-nm equivalent oxide thicknesses of the gate insulating films, and various channel widths. The results show that the influence of the gate electrode on the sides of the channel increases as the channel width is reduced, which leads to excellent OFF-state and ON-state current characteristics of the FET with a 51-nm channel length and a 50-nm channel width. By exploiting these characteristics, low-power large-scale integration (LSI) applications become possible that would not be possible with conventional Si-LSI techniques.

Emerging nonvolatile memory with an oxide-semiconductor-based thin-film transistor (TFT) using indium-gallium-zinc-oxide (IGZO) was developed. The memory is called nonvolatile oxide-semiconductor random access memory (NOSRAM). The memory cell of the NOSRAM (NOSRAM cell) consists of an IGZO TFT for data writing, a normal Si-based p-channel metal-oxide-semiconductor (PMOS) for data reading, and a cell capacitor for storing charge and controlling the PMOS gate voltage. The IGZO TFT and the cell capacitor are formed over the PMOS. Owing to extremely low-leakage-current characteristics of the IGZO TFT, the charge stored in the 2-fF cell capacitor is maintained for a long time. This long data retention realized innovative nonvolatile memory. The NOSRAM cell fabricated with the 0.8-μ m process technology demonstrated an on/off ratio of 107 and an endurance over 1012 write cycles. In addition, NOSRAM with a memory capacity of 1 Mb was fabricated; the cell size was 12.32 μm2 and the cell array size was 13.5 mm2. The 1-Mb NOSRAM achieved basic operation at 4.5 V or less, write operation at 150 ns/page, read distribution of data “1” with 3σ = 0.10 V, and a data retention over 60 days at 85°C.

We report the world's smallest field effect transistors (FETs) with channel lengths of 32 nm including c-axis aligned crystalline (CAAC) In-Ga-Zn-O as their active layers, which achieve low off-state leakage currents. Furthermore, these FETs exhibit excellent subthreshold swing values despite having thick gate insulating film. The FET operation has been achieved owing to the 3D gate structure with a thin active layer, due to the FETs being accumulation-type FETs with intrinsic channels, and due to the dielectric anisotropy of the CAAC crystal structure.

We report novel FETs with a structure in which not only the top surface but also the side surfaces of island-shaped c-axis aligned crystalline indium-gallium-zinc oxide (CAAC-IGZO) serving as a channel are surrounded by a gate electrode, that is, surrounded channel CAAC-IGZO FETs. The FETs maintained their favorable subthreshold characteristics even if the channel length was scaled down to approximately 50 nm, i.e., normally-off, DIBL of 67 mV/V, SS of 92 mV/dec, and an off-state current lower than the measurement limit (0.1 pA) for a gate insulating film EOT of 11 nm. Moreover, we applied an FET with such a structure to a memory and discussed the writing time and the retention time, which were expected to be less than 5 ns and greater than 1,000 sec, respectively, for storage capacitance of 1 fF from circuit simulation.

A chip of embedded SRAM having backup circuits using a 60-nm c-axis aligned crystalline oxide semiconductor (CAAC-OS) such as CAAC indium-gallium-zinc oxide (CAAC-IGZO) and Cortex-M0 core having flip-flops with CAAC-OS backup circuits is fabricated. The SRAM and M0 core can retain data using the backup circuits during power-off; thus, they can perform power gating (PG) with backup time of 100 ns and recovery time of 10 clock cycles (including data restoration time (100 ns)). Further, memory cell area and performance in combining a 45-nm Si SRAM memory cell with 60-nm CAAC-OS are estimated to have negligible overhead.

A multi-context (MC) field-programmable gate array (FPGA) enabling fine-grained power gating (PG) is fabricated by a hybrid process involving a 1.0 ?m c-axis aligned crystalline In?Ga?Zn?O (CAAC-IGZO) field-effect transistor (FET), which is one of CAAC oxide-semiconductor (OS) FETs, and a 0.5 ?m complementary metal oxide semiconductor (CMOS) FET. The FPGA achieves a 20% layout area reduction in a routing switch and an 82.8% reduction in power required to retain data of configuration memory (CM) cells at 2.5 V driving compared to a static random access memory (SRAM)-based FPGA. A controller for fine-grained PG can be implemented at an area overhead of 7.5% per programmable logic element (PLE) compared to a PLE without PG. For each PLE, the power overhead with fine-grained PG amounts to 2.25 and 2.26 nJ for power-on and power-off, respectively, and break-even time (BET) is 19.4 ?s at 2.5 V and 10 MHz driving.

Crystalline In-Ga-Zn Oxide (IGZO) including c-axis aligned crystal (CAAC) enables FETs to show high reliability and extremely low off-state current. CAAC-IGZO technology is expected to grow to main technology of next-generation displays and is already contributing to mass-production of liquid crystal displays. In this paper by focusing on a very important feature of CAAC-IGZO FET, extremely low off-state current, its pioneering various applications to LSI are reviewed and discussed. In particular, a success in development of a hybrid process of CMOS FETs and CAAC-IGZO FETs promotes our developments of novel memories, processors, image sensors, and recently, field programmable gate arrays (FPGA).

To achieve both low power consumption and high-speed operation, we fabricated c-axis-aligned crystalline indium–gallium–zinc oxide (CAAC-IGZO) field-effect transistors (FETs) with In-rich IGZO and common IGZO ( in atomic ratio) active layers through a simple process using trench gates, and evaluated their characteristics. The results confirm that 60-nm-node IGZO FETs fabricated through a 450 °C process show an extremely low off-state current below the detection limit (at most 2 × 10−16 A) even at a measurement temperature of 150 °C. The results also reveal that the FETs with the In-rich IGZO active layer show a higher on-state current than those with the common IGZO active layer and have excellent frequency characteristics with a cutoff frequency and a maximum oscillation frequency of up to 20 and 6 GHz, respectively. Thus, we demonstrated that CAAC-IGZO FETs with trench gates are promising for achieving both low power consumption and high-speed operation.

We fabricated a dynamic random access memory (DRAM) using crystalline oxide semiconductor (OS) transistors and not requiring refresh for more than ten days. We call this memory a dynamic oxide semiconductor random access memory (DOSRAM). A crystalline oxide semiconductor is an In-Ga-Zn-oxide (IGZO) semiconductor and has a c-axis aligned crystal (CAAC) structure. A crystalline OS transistor has extremely low off-state current. The DOSRAM uses this device for access transistors, and can have a very long refresh cycle. A memory cell array made of a crystalline OS layer can be stacked on peripheral circuits made of a silicon (Si) semiconductor layer; thus, the area of the DOSRAM can be decreased.

Field-effect transistors (FETs) with c-axis-aligned crystalline In–Ga–Zn–O (CAAC-IGZO) active layers have extremely low off-state leakage current. Exploiting this feature, we investigated the application of CAAC-IGZO FETs to LSI memories. A high on-state current is required for the high-speed operation of these LSI memories. The field-effect mobility μFE of a CAAC-IGZO FET is relatively low compared with the electron mobility of single-crystal Si (sc-Si). In this study, we measured and calculated the channel length L dependence of μFE for CAAC-IGZO and sc-Si FETs. For CAAC-IGZO FETs, μFE remains almost constant, particularly when L is longer than 0.3 µm, whereas that of sc-Si FETs decreases markedly as L shortens. Thus, the μFE difference between both FET types is reduced by miniaturization. This difference in μFE behavior is attributed to the different susceptibilities of electrons to phonon scattering. On the basis of this result and the extremely low off-state leakage current of CAAC-IGZO FETs, we expect high-speed LSI memories with low power consumption.

A dynamic oxide semiconductor random access memory (DOSRAM) array that achieves reduction in storage capacitance (Cs) and decrease in refresh rate has been fabricated by using a c-axis aligned crystalline oxide semiconductor (CAAC-OS) transistor (L = 60 nm) with an extremely low off-state current. We have confirmed that this array, composed of cells that include a CAAC-OS transistor with W/L = 40 nm/60 nm using InGaZnO and a 3.9 fF storage capacitor, operates with write and read times of 5 ns. Therefore, DOSRAM can ensure sufficient Cs while maintaining operation speed comparable to that of dynamic random access memory (DRAM). We have found that the read signal voltage of DOSRAM is changed by approximately 30 mV after 1 h at 85 °C. Thus, DOSRAM is a promising replacement for DRAM.

Using data retention circuits that include crystalline oxide semiconductor transistors as backup circuits for power gating, a processor system can reduce standby leakage current significantly. This is effective in the Internet of Things (IoT) applications that require standby power reduction. The crystalline oxide semiconductor transistor can constitute a nonvolatile data retention circuit easily because it exhibits significantly lower off-state current than a silicon transistor and is highly compatible with a CMOS logic circuit. The backup circuit can achieve 2-clock-cycle data backup and 4-clock-cycle data restore; thus, the processor system can efficiently perform temporally fine-grained power gating and can achieve longer standby times. Furthermore, area overheads due to the backup circuits are kept very small because the crystalline oxide semiconductor transistors are stacked on silicon transistors.

A multi-context (MC) field-programmable gate array (FPGA) enabling fine-grained power gating (PG) is fabricated by a hybrid process involving a 1.0 µm c-axis aligned crystalline In–Ga–Zn–O (CAAC-IGZO) field-effect transistor (FET), which is one of CAAC oxide-semiconductor (OS) FETs, and a 0.5 µm complementary metal oxide semiconductor (CMOS) FET. The FPGA achieves a 20% layout area reduction in a routing switch and an 82.8% reduction in power required to retain data of configuration memory (CM) cells at 2.5 V driving compared to a static random access memory (SRAM)-based FPGA. A controller for fine-grained PG can be implemented at an area overhead of 7.5% per programmable logic element (PLE) compared to a PLE without PG. For each PLE, the power overhead with fine-grained PG amounts to 2.25 and 2.26 nJ for power-on and power-off, respectively, and break-even time (BET) is 19.4 µs at 2.5 V and 10 MHz driving.

A channel length of a c-axis aligned crystal indium gallium zinc oxide (CAAC-IGZO) transistor having low off-state current at a yA/µm level was decreased to 100 nm, and the electrical characteristics and short-channel effect of the CAAC-IGZO transistor were researched. As a result, we found that, in the CAAC-IGZO transistor with L = 100 nm, even with a gate insulator film having an equivalent oxide thickness (EOT) = 11 nm, an extremely small off-state current of 380 yA/µm at 85 °C is maintained, in addition channel length dependence of the electrical characteristics is hardly seen. Favorable values of characteristics of the CAAC-IGZO transistor can be obtained, such as subthreshold slope (SS) = 77 mV/dec, drain induced barrier lowering (DIBL) = 73 mV/V, threshold voltage (V th) = 0.65 V, and on-state current (I on) = 65 µA/µm. These results suggest the possibility that the CAAC-IGZO transistor can be applied to an LSI in a deep submicron region.