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The interface between dielectric and organic semiconductor is critically important in determining organic thin‐film transistor (OTFT) performance. Surface polarity of the dielectric layer can hinder charge transport characteristics, which has restricted utilization of polymeric dielectric materials containing polar functional groups. Herein, the electrical characteristics of OTFTs are analyzed depending on the alkyl chain length of organic semiconductors and surface polarity of polymer dielectrics. High‐performance dibenzothiopheno[6,5‑b:6′,5′‑f]thieno[3,2‑b]thiophene (DBTTT) and newly synthesized its alkylated derivatives (C6‐DBTTT and C10‐DBTTT) are utilized as organic semiconductors. As dielectric layers, non‐polar poly(1,3,5‐trimethyl‐1,3,5‐trivinylcyclitrisiloxane) (pV3D3) and poly(2‐cyanoethyl acrylate‐co‐diethylene glycol divinyl ether) [p(CEA‐co‐DEGDVE)] with polar cyanide functionality are utilized. The fabricated OTFTs with pV3D3 commonly exhibit the excellent charge transport characteristics. In addition, the OTFT performance is improved with lengthening the alkyl chain in organic semiconductors, which can be attributed to the molecular orientation of semiconductors. On the other hand, non‐alkylated DBTTT OTFTs with polar p(CEA‐co‐DEGDVE) show relatively poor electrical characteristics, while their performance is drastically enhanced with the alkylated DBTTTs. The ultraviolet photoelectron spectroscopy (UPS) reveals that surface polarity of the dielectric layer can be abated with alkyl chain in organic semiconductors. It is believed that this study can provide a useful insight to optimize dielectric/semiconductor interface to achieve high‐performance OTFTs. [ABSTRACT FROM AUTHOR]

We report a novel platform on which we design a flexible high-performance complementary metal–oxide–semiconductor (CMOS) inverter based on an inkjet-printed polymer PMOS and a two-dimensional (2D) multilayer molybdenum disulfide (MoS 2 ) NMOS on a flexible substrate. The initial implementation of a hybrid complementary inverter, comprised of 2D MoS 2 NMOS and polymer PMOS on a flexible substrate, demonstrates a compelling new pathway to practical logic gates for digital circuits, achieving extremely low power consumption with low sub-1 nA leakage currents, high performance with a voltage gain of 35 at 12 V supply voltage, and high noise margin (larger than 3 V at 12 V supply voltage) with low processing costs. These results suggest that inkjet-printed organic thin film transistors and 2D multilayer semiconducting transistors may form the basis for potential future high performance and large area flexible integrated circuitry applications. [ABSTRACT FROM AUTHOR]