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Advances in performance of integrated circuits has throughout history been linked to minituarization of front-end-of-line (FEOL) devices, such as transistors. Three dimensional stacked integrated circuits (3D SIC) present a potential technology that can enhance system performance based on interconnect and packaging techniques. Contemporary vertical stacking of Si chips in 3D SIC technology is based on through-Si vias and microbumps. Compared to two dimensional integrated circuits, these vertical interconnects enable shorter signal paths that lead to lower signal delay and reduced power consumption. Extensive research is being done on the electrical properties of TSVs and microbumps. Furthermore, the thermo-mechanical impact of TSVs on the back-end-of-line (BEOL) and Si is being investigated. However, little is known about the thermo-mechanical impact of chip-package interaction (CPI) on Si in 3D SIC technology. Therefore, this thesis focuses on detecting mechanical stress mechanisms occuring after 3D IC stacking and packaging and the impact of those stresses on FEOL devices in Si.Within this thesis, the linear piezoresistance model, originally developed for bulk Si, is applied to describe the response of FEOL devices to stress. In this case, the piezocoefficients represent the stress sensitivity of the whole device, rather than bulk material.A stress sensor evaluation methodology is proposed and implemented within the thesis. Stress sensitivity of several FEOL device types and through several FEOL technology nodes was assessed. FEOL devices were calibrated to in-plane and out-of-planestress. The stress sensitivities are analyzed from two perspectives: To gain information on the nature of stress sensitivity of FEOL devices and itstrends through scaling technology nodes Their applicability for usage as FEOL CPI stress sensorsObtained FEOL device piezocoefficients can greatly differ from Smith piezocoefficients for bulk Si. Direct calibration of FEOL devices to stress is necessary.The stress sensitivity of MOSFETs, FinFETs and pseudo-Hall devices was assessed.All of these devices exhibit a sensitivity to mechanical stress. MOSFETs were implemented as stress sensors. An important advantage of MOSFETs is its ability toextract individual stress components. FinFETs exhibited lower sensitivity to stress than MOSFETs. Pseudo-Hall devices exhibit better temperature stability than MOSFETs, but extraction of stress components is not straightforward. Under certain conditions, MOSFETs can be used to extract both in-plane stresses and out-of-plane stress.High MOSFET current shift of above 40% was observed after 3D Si die stacking and linked to the underfill-microbump stress mechanism. During cooling of a 3D IC stack after die bonding, the underfill as the material with the highest coefficient of thermal expansion (CTE) in the surrounding, shrinks and pulls the thin Si die over the underlying microbumps causing local warpage of the thin Si die. The underfill microbump stress mechanism is a CTE mismatch driven mechanism initiated by the underfill material.The underfill-microbump interaction was experimentally monitored on 3 generations of 2-die 3D stacks. Global and local in-plane and out-of-plane stresses generated after 3D stacking were extracted with MOSFETs on both die levels. Stress in Si was monitored on the opposite side of the microbumps, directly below the microbump and between microbumps. After 3D die stacking, on the opposite side of the microbump, tensile in-plane stress components in Si are dominant. Compressive out-of-plane stress becomes dominant on the Si side below the microbump. Cu pads used for creating microbumps leave a non-negligible stress mark in Si as well.N-type and p-type Si and in that sense n-type and p-type MOSFETs have a distinctively different response to mechanical stress. Circular stress patterns are observed in Si as a consequence of the underfill-microbump interaction, which reflect into circular current shift patterns for n-type Si devices and orbital current shift patterns with positive and negative current shift regions for p-type Si devices. Keep-out zones, prohibited areas in Si for processing MOSFETS and other sensitive FEOL devices on IC layouts due to the underfill-microbump stress impact, are proposed. Circular keep-out zones, primarily above the microbump position are proposed for n-type devices. Rectangular keep-out zones around the microbump position, in the surrounding but not directly above the microbump position, are proposed for p-type devices.Underfill-microbump stress mitigation guidelines are proposed based on an experimentally validated finite element model. Increasing die thickness, choosing a lowstress underfill, decreasing the pitch between microbumps, decreasing the microbump height and grouping microbumps in larger arrays all contribute to stress reduction in Si. Based on implementation of some of the guidelines, such as increase of Si thickness and lower microbump pitch, stress decrease in Si is observed through assessed 3D stack generations, from a starting 827 MPa down to 125 MPa.3D stacks were further packaged. Global and local in-plane and out-of-plane stress in Si generated after 3D stack packaging was extracted with MOSFETs on both die levels. It was revealed that the package substrate has an equally important impact in generating Si stress and package warpage as the mold compound. The final package warpage and Si stress is a result of the interaction of the substrate and mold compound.Packaging exerts different global stress patterns on the two stacked Si dies. Between the microbumps, compressive in-plane stress is observed on the thinned die and tensile in-plane stress is observed on the thicker die. High out-of-plane stress is observed between the microbumps on the thicker Si die. Local sensors revealed that stress patterns in Si from the underfill-microbump reaction remain after packaging andare only modified in absolute value by the interaction of the substrate and mold compound. Contents Acknowledgments 3 Abstract 5 Nederlandse Samenvatting 7 List of acronyms 9 List of Figures 11 List of Tables 23 1 Introduction 29 1.1 Thesis objective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.2 Thesis outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2 State of the art and beyond 33 2.1 Brief history of 3D integrated circuits . . . . . . . . . . . . . . . . . 34 2.1.1 Idea of verticality . . . . . . . . . . . . . . . . . . . . . . . . 34 2.1.2 Evolution and diversity of 3D IC technology . . . . . . . . . 37 2.1.3 Contemporary setting of the thesis . . . . . . . . . . . . . . . 43 2.2 Literature overview on CPI in 3D IC technologies . . . . . . . . . . . 45 2.2.1 3D stacking and packaging . . . . . . . . . . . . . . . . . . . 47 2.2.1.1 TSV impact . . . . . . . . . . . . . . . . . . . . . 47 2.2.1.2 3D IC stacking options . . . . . . . . . . . . . . . 49 2.2.1.3 3D IC CPI . . . . . . . . . . . . . . . . . . . . . . 56 2.2.2 Stress sensors . . . . . . . . . . . . . . . . . . . . . . . . . . 64 2.3 Contribution of this thesis . . . . . . . . . . . . . . . . . . . . . . . 73 2.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 3 Piezoresistance effect and Stress sensor evaluation 75 3.1 Piezoresistance effect . . . . . . . . . . . . . . . . . . . . . . . . . . 76 3.1.1 Fundamentals of the piezoresistance effect . . . . . . . . . . 76 3.1.2 Justification of usage . . . . . . . . . . . . . . . . . . . . . . 81 3.1.3 Twofoldness . . . . . . . . . . . . . . . . . . . . . . . . . . 83 25 CONTENTS 3.2 Stress sensor evaluation . . . . . . . . . . . . . . . . . . . . . . . . . 85 3.2.1 Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . 85 3.2.2 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 3.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 4 Methods and techniques 95 4.1 Finite element method . . . . . . . . . . . . . . . . . . . . . . . . . 96 4.1.1 Basic description . . . . . . . . . . . . . . . . . . . . . . . . 96 4.1.2 Usage in this thesis . . . . . . . . . . . . . . . . . . . . . . . 97 4.2 Delaminator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 4.2.1 Basic description . . . . . . . . . . . . . . . . . . . . . . . . 98 4.2.2 Usage in thesis . . . . . . . . . . . . . . . . . . . . . . . . . 100 4.2.3 4-point bending . . . . . . . . . . . . . . . . . . . . . . . . . 100 4.2.3.1 Sample preparation 4-point bending stress calibration 100 4.3 Nano-indenter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 4.3.1 Basic description . . . . . . . . . . . . . . . . . . . . . . . . 105 4.3.2 Usage in this thesis . . . . . . . . . . . . . . . . . . . . . . . 105 4.3.3 Sample preparation . . . . . . . . . . . . . . . . . . . . . . . 107 4.4 Profilometers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 4.4.1 Basic description . . . . . . . . . . . . . . . . . . . . . . . . 108 4.4.2 Optical profilometer . . . . . . . . . . . . . . . . . . . . . . 108 4.4.3 Mechanical profilometer . . . . . . . . . . . . . . . . . . . . 109 4.4.4 Transformation of warpage to stress . . . . . . . . . . . . . . 112 4.5 X-ray diffraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 4.5.1 Basic description . . . . . . . . . . . . . . . . . . . . . . . . 113 4.5.2 XRD-3DSM technique . . . . . . . . . . . . . . . . . . . . . 114 4.6 Test vehicles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 4.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 5 Impact of mechanical stress on the Front-End-of-Line 121 5.1 Impact of mechanical stress on scaling technology nodes . . . . . . . 122 5.2 Planar transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 5.2.1 In-plane stress sensitivity . . . . . . . . . . . . . . . . . . . . 127 5.2.2 Out-of-plane stress sensitivity . . . . . . . . . . . . . . . . . 136 5.2.3 Extracting in-plane stress . . . . . . . . . . . . . . . . . . . . 141 5.3 Assessment of stress impact on advanced devices . . . . . . . . . . . 145 5.3.1 FinFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 5.3.2 Pseudo-Hall stress sensors . . . . . . . . . . . . . . . . . . . 150 5.4 Biaxial stress test . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 5.5 High temperature calibration . . . . . . . . . . . . . . . . . . . . . . 158 5.6 High stress calibration . . . . . . . . . . . . . . . . . . . . . . . . . 162 5.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 6 Back-End-of-Line out-of-plane stress sensors 167 6.1 Out-of-plane stress sensors . . . . . . . . . . . . . . . . . . . . . . . 168 6.2 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 7 3D stacked ICs 175 7.1 Basics of the underfill-microbump interaction mechanism . . . . . . . 176 7.2 Impact on 3D IC layout . . . . . . . . . . . . . . . . . . . . . . . . . 183 7.3 Underfill-microbump stress mitigation guidelines . . . . . . . . . . . 188 7.3.1 Parametric study . . . . . . . . . . . . . . . . . . . . . . . . 188 7.3.2 Underfill selection . . . . . . . . . . . . . . . . . . . . . . . 190 7.3.3 Impact of stack geometry . . . . . . . . . . . . . . . . . . . . 194 7.3.4 Si etch ring . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 7.3.5 Ranking of stress reduction parameters . . . . . . . . . . . . 201 7.4 Investigation of stress mitigation on test chips . . . . . . . . . . . . . 205 7.4.1 Test chips for 3D IC stacking . . . . . . . . . . . . . . . . . . 205 7.4.2 PTCQ stress test chip design . . . . . . . . . . . . . . . . . . 205 7.4.3 3D stack design comparison . . . . . . . . . . . . . . . . . . 210 7.4.4 FUJI 3D stack results . . . . . . . . . . . . . . . . . . . . . . 211 7.4.4.1 FUJI 3D stack at room temperature . . . . . . . . . 211 7.4.4.2 FUJI 3D stack at elevated temperatures . . . . . . . 216 7.4.5 PTCQ 3D stacks results . . . . . . . . . . . . . . . . . . . . 222 7.4.5.1 Global stress . . . . . . . . . . . . . . . . . . . . . 225 7.4.5.2 Local stress . . . . . . . . . . . . . . . . . . . . . 225 7.4.6 Stress evolution - from ETNA to FUJI and PTCQ . . . . . . . 234 7.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 8 2D and 3D packaging 239 8.1 Impact of packaging in 2D technology . . . . . . . . . . . . . . . . . 240 8.2 2D wirebonded package . . . . . . . . . . . . . . . . . . . . . . . . 240 8.3 2D BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 8.4 Stress build up in a 3D stacked IC package . . . . . . . . . . . . . . . 246 8.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 9 General conclusions and future work 259 9.1 General conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 9.1.1 Initial objectives and final contributions . . . . . . . . . . . . 260 9.1.2 Evaluation of FEOL devices as CPI stress sensors . . . . . . 261 9.1.3 Analysis of mechanical stress in 3D stacked ICs . . . . . . . . 264 9.1.4 Analysis of stress in 3D stacked IC packages . . . . . . . . . 266 9.2 Recommendations for future work . . . . . . . . . . . . . . . . . . . 268 Bibliography 270 List of publications 280 In cooperation with imec Belgium, Kapeldreef 75, 3001 Leuven, Belgium nrpages: 282 status: published