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This letter presents a construction flow for rate-compatible LDPC (RC-LDPC) codes, collaboratively using both extension and splitting schemes. In addition to the decoding threshold used for selecting the degree distribution, a new metric, known as the Average ACE ($A^{2}CE$) value, is introduced in order to estimate the Tanner graph connectivity. The proposed collaborative scheme provides more flexibility in the designs of the degree distribution and graph connectivity, both of which are critical for RC LDPC codes that have short and/or moderate lengths. The designed LDPC codes achieve a comparable or better error rate performance compared to existing codes. [ABSTRACT FROM AUTHOR]

This letter presents a low-complexity redecoding-based error-floor lowering technique for quasi-cyclic low-density parity-check codes, where a predetermined set of variable nodes are attenuated before the redecoding. Using a two-stage off-line search, the attenuation set is determined based on the error patterns collected from the standard decoding simulation. It is shown that the error floor can be effectively lowered, and only a negligible amount of complexity is introduced. [ABSTRACT FROM AUTHOR]

This paper presents an efficient combined bit-flipping (BF) and stochastic low-density parity-check decoder, where a BF decoder is used to achieve a reduction in decoding cycles. A node-wise probability tracer is adopted at each variable node (VN) in order to achieve a BER performance comparable to the normalized min-sum algorithm, where check-to-variable (C2V) messages are used as inputs, rather than the variable-to-check (V2C) messages adopted in previous stochastic decoders. The complexity of the VN units is greatly reduced by sharing common units used in the generation of V2C messages together with a probability tracer. The C2V-based probability tracer enables the design of a decoder that provides a short critical path. The proposed methods are demonstrated by designing a (2048, 1723) decoder that is implemented in a 90 nm process. A total of 1460 K logic gates are integrated in a decoder that has an area of 4.12 \mboxmm^2 and achieves a coded throughput of 39.3 Gb/s at a clock frequency of 749 MHz. To the best of the authors’ knowledge, the proposed decoder achieves the best normalized throughput-to-area ratio among the stochastic decoders reported in the open literatures. [ABSTRACT FROM AUTHOR]

This paper presents a high-throughput, energy-efficient, and scalable low-density parity-check (LDPC) decoder with time-domain (TD) signal processing. The proposed arbiter-based minimum value finder is able to support practical long codes. The latency for determining the first two minimum values required in the check node unit is significantly reduced through TD processing. A layered Q -based decoding architecture together with the associated scheduling is proposed in order to reduce the amount of memory used for check node storage. Multimode operations are supported by leveraging the structure of the base matrices and the proposed scalable minimum finder architecture. As a proof of concept, a TD-based multimode LDPC decoder for high-speed IEEE 802.15.3c is designed and fabricated in a 90-nm CMOS process. The LDPC decoder integrates 495k logic gates in 2.25 mm2 and achieves a throughput of 5.28 Gb/s at 157 MHz from a 1.05 V supply voltage. The power and normalized energy dissipation are 182 mW and 34.47 pJ/b, respectively. The proposed LDPC decoder is more hardware and energy efficient than previous digital counterparts and is able to support long codes for practical applications, which is still infeasible for the state-of-the-art TD-based LDPC decoders. [ABSTRACT FROM AUTHOR]

Aimed at the emerging massive multiple-input multiple-output (MIMO) systems, both hard-decision and soft-decision detectors are investigated for the generalized space shift keying (GSSK) modulation scheme, where a codebook-assisted technique is used to reduce the tree-search complexity. Furthermore, the outer low-density parity-check (LDPC) code is optimized such that the proposed system design can provide an error performance, which is almost the same as that of the scheme that uses the maximum a posteriori (MAP) soft detector, but with a much lower computational complexity. [ABSTRACT FROM PUBLISHER]

In this paper, a low-density parity-check (LDPC) coded recording system is investigated, for which the run-length-limited (RLL) constraint is satisfied by deliberate flipping at the write side and by estimating the flipped bits at the read side. Two approaches are proposed for enhancing the error performance of such a system. The first approach is to alleviate the negative effect of incorrect estimation of the flipped bits by adjusting the soft information. The second approach is to increase the likelihood of the correct detection of flipped bits by designing a flipped-bit detection algorithm that utilizes both the RLL constraint and the parity-check constraint of the LDPC code. These two approaches can be combined to obtain significant improvement in performance over previously proposed methods. [ABSTRACT FROM AUTHOR]