5 results on '"Agarwal, Alpana"'
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2. A 1 μs Locking Time Dual Loop ADPLL with Foreground Calibration-Based 6 ps Resolution Flash TDC in 180 nm CMOS.
3. A Wide Frequency Range Low Jitter Integer PLL with Switch and Inverter Based CP in 0.18 μm CMOS Technology.
4. A 2.3 mW Multi-Frequency Clock Generator with −137 dBc/Hz Phase Noise VCO in 180 nm Digital CMOS Technology.
5. A fast locking and low jitter hybrid ADPLL architecture with bang bang PFD and PVT calibrated flash TDC.
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