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We report on the design of an active feedback circuit for charge sensitive amplifiers used for reading out hybrid pixel detectors. The predominant advantages of the proposed feedback over the existing solutions are its low noise, stability, and tunability. In addition, the circuit occupies small silicon area, which is crucial for hybrid pixel detectors. This paper presents both the mathematical analysis of the proposed circuit and measurement results obtained with the test structure.

X-ray photon correlation spectroscopy is performed using a dual counter pixel array detector at a frame rate of 11.8 kHz with no readout dead-time., Small-angle scattering X-ray photon correlation spectroscopy (XPCS) studies were performed using a novel photon-counting pixel array detector with dual counters for each pixel. Each counter can be read out independently from the other to ensure there is no readout dead-time between the neighboring frames. A maximum frame rate of 11.8 kHz was achieved. Results on test samples show good agreement with simple diffusion. The potential of extending the time resolution of XPCS beyond the limit set by the detector frame rate using dual counters is also discussed.

This paper presents a readout integrated circuit called UFXC32k, designed for hybrid pixel semiconductor detectors used in X-ray imaging applications. The UFXC32k integrated circuit, designed in a CMOS 130 nm process, contains about 50 million transistors in the area of $9.64\;\hbox{mm} \times 20.15\;\hbox{mm}$ . The core of the IC is a matrix of $128 \times 256$ square-shaped pixels of ${\hbox{75}}\;\mu\hbox{m}$ pitch. Each pixel contains a charge sensitive amplifier, a shaper, two discriminators, and two 14-bit ripple counters. The analog front-end electronics allow processing of sensor signals of both polarities (holes and electrons). The UFXC32k chip is bump-bonded to a pixel silicon sensor and is fully characterized using X-ray radiation. The measured equivalent noise charge for the standard settings is equal to $123\ {{\rm e}^ - }\;\hbox{rms}$ (for the peaking time of 40 ns) and each pixel dissipates $26\;\mu\hbox{W}$ . Thanks to the use of trim blocks working in each pixel independently, an effective offset spread calculated to the input is only $9\ {{\rm e}^ - }\;\hbox{rms}$ with a gain spread of 2%. The maximum count rate per pixel depends mainly on effective CSA feedback resistance. Dead time in the front end can be set as low as 85 ns. In the continuous readout mode, a user can select the number of bits read out from each pixel to optimize the UFXC32k frame rate, e.g., for a readout of 2 bits/pixel with 200 MHz clock, the frame rate is equal to 23 kHz.

We report on a novel technique of an in-pixel multilevel offset correction to be used in hybrid pixel detector readout circuits operating in a single photon counting mode. This technique was implemented in a prototype integrated circuit consisting of 23,552 square shaped pixels of $75\ \mu \hbox{m}$ pitch, which was designed and manufactured in CMOS 130 nm technology. Each pixel contains a charge sensitive amplifier, shaper, two discriminators, two 14-bit counters and a block for multilevel offset correction. The effective gain and offset are controlled individually in each pixel. The measurement results prove very good uniformity of the prototype integrated circuit with an offset spread of only 7 ${{\rm e}^ - }{\rm rms}$ and a gain spread of 2.5%.

The paper presents a prototype integrated circuit built in a 40 nm CMOS process for readout of a hybrid pixel detector. The core of the IC constitutes a matrix of $18 \times 24$ pixels with the pixel size of $100~\mu\hbox{m} \times 100~\mu\hbox{m}$ . The paper explains the functionality and the architecture of the IC, which is designed to operate in both the standard single photon counting mode and the single photon counting mode with interpixel communication to mitigate negative effects of charge sharing. This article focuses on the measurement results of the IC operating in the standard single photon counting mode. The measured ENC is $84{\rm e}^{-}~\hbox{rms}$ (for the peaking time of 48 ns), the gain is $79.7~\mu\hbox{V}/{\rm e}^{-}$ , while the effective threshold dispersion is $21{\rm e}^{-}~\hbox{rms}$ .

International audience; Substantial experimental and theoretical efforts worldwide are devoted to explore the phase diagram of strongly interacting matter. At LHC and top RHIC energies, QCD matter is studied at very high temperatures and nearly vanishing net-baryon densities. There is evidence that a Quark-Gluon-Plasma (QGP) was created at experiments at RHIC and LHC. The transition from the QGP back to the hadron gas is found to be a smooth cross over. For larger net-baryon densities and lower temperatures, it is expected that the QCD phase diagram exhibits a rich structure, such as a first-order phase transition between hadronic and partonic matter which terminates in a critical point, or exotic phases like quarkyonic matter. The discovery of these landmarks would be a breakthrough in our understanding of the strong interaction and is therefore in the focus of various high-energy heavy-ion research programs. The Compressed Baryonic Matter (CBM) experiment at FAIR will play a unique role in the exploration of the QCD phase diagram in the region of high net-baryon densities, because it is designed to run at unprecedented interaction rates. High-rate operation is the key prerequisite for high-precision measurements of multi-differential observables and of rare diagnostic probes which are sensitive to the dense phase of the nuclear fireball. The goal of the CBM experiment at SIS100 ( $\sqrt{s_{NN}}=$ 2.7--4.9 GeV) is to discover fundamental properties of QCD matter: the phase structure at large baryon-chemical potentials ( $\mu_B > 500$ MeV), effects of chiral symmetry, and the equation of state at high density as it is expected to occur in the core of neutron stars. In this article, we review the motivation for and the physics programme of CBM, including activities before the start of data taking in 2024, in the context of the worldwide efforts to explore high-density QCD matter.

W artykule został przedstawiony projekt przetwornika analogowo-cyfrowego w technologii CMOS 180nm. Wybraną architekturą jest przetwornik kompensacyjny z równoważeniem ładunku. Duży nacisk został położony na zmniejszenie zajmowanej powierzchni jak i minimalizację poboru mocy, co czyni prezentowany układ odpowiednim do zastosowań wielokanałowych. Autorzy prezentują wyniki symulacji Monte-Carlo nieliniowości charakterystyki przejściowej. Zaprezentowany przetwornik osiąga szybkość konwersji 3 MS/s przy rozdzielczości 7 bitów i poborze mocy 77 μW oraz zajmuje tylko 90 x 95 μm2.

A 64-channel ASIC (SXDR64) aimed to work with both AC and DC coupled detectors (Si, CdTe, GaAs), in a single photon counting mode with an energy window has been developed. Every channel of the ASIC consists of a charge sensitive amplifier, a pole-zero cancellation circuit, a 4th order shaper with programmable gain from 14 μV/e- to 50 μV/e- and peaking time from 115 ns to 380 ns, a base-line restorer, two independent discriminators, and two 20-bit counters. Control and readout of the chip are done using on-chip LVDS drivers/receivers. The ASIC can work with input leakage currents in the range from -10 nA up to 7 nA. The ENC obtained with an AC-coupled Si detector is 120 e- for a peaking time Tp=115 ns and Cdet=1.2 pF. With a DC-coupled CdTe detector, the ENC is 210 e- rms for a peaking time Tp=380 ns and Cdet=2 pF and the leakage current Idleak=0.15 nA. The implemented trim DACs at the discriminator inputs allows to minimize the effective threshold spread to 8 e- rms (at one sigma level). The ASIC is designed in a CMOS 0.35 μm technology and its total area is 4800×5000 μm2.

The paper presents a readout integrated circuit called UFXC32k designed for hybrid pixel semiconductor detectors used in X-ray imaging applications. The UFXC32k integrated circuit designed in CMOS 130 nm process, contains about 50 million transistors in the area of 9.64 mm × 20.15 mm. The core of the IC is the matrix of 128 × 256 square shaped pixels of 75 μm pitch. Each pixel contains a charge sensitive amplifier, a shaper, a discriminator, correction circuits and two 14-bit counters. The data is read out via 8 Low Voltage Differential Signaling (LVDS) outputs. The UFXC32k chip is bump-bonded to a pixel silicon sensor and fully characterized in X-ray radiation. The measured equivalent noise charge is equal to 123 e− rms (for the peaking time of 40 ns) and each pixel dissipates 26 μW. Thanks to the use of multilevel offset correction, an effective offset spread calculated to the input is only 9 e− rms with the gain spread of 2 %.

We report on the design of an integrated circuit operating in a single photon counting mode for readout of hybrid pixel detectors. The prototype IC was designed and fabricated in CMOS 130 nm technology and consists of 23552 square shaped pixels of 75 µm pitch. Each pixels consists of charge sensitive amplifier, shaper, two discriminators and two 14-bit counters. Additionally each pixel contains also novel key blocks for offset and gain trimming. The prototype IC works with two energy thresholds in the readout mode separate from exposure. In a continuous mode (with a zero dead time) the IC operates with single threshold. The readout pixel has an equivalent noise charge of 89 e- rms and dissipates only 25 µW. Tests prove exceptional uniformity of IC: an offset spread below 12e- rms and a gain spread of only 3%.

We report on the novel method of an in-pixel offset and gain correction for implementation in multichannel hybrid detector readout circuits. A prototype ASIC consisting of 23552 square shaped pixels of 75 µm pitch was designed and fabricated in CMOS 130 nm technology. Each pixel containing charge sensitive amplifier, shaper, discriminator, correction circuits and two 14-bit counters has an equivalent noise charge of 89 e− rms and dissipates only 25 µW. Tests prove its exceptional uniformity with an offset spread of 19e− rms and the gain spread of only 3%, rms what is good enough for color X-Ray imaging. The paper presents the architecture of the ASIC, a transistor level novel schematic of key blocks used for offset and gain trimming, the testing procedure and its results.

For many years hybrid pixel detectors working in the single photon counting mode have been used not only in high energy physics experiments but also for X-ray imaging applications. In these detectors each pixel has its independent electronic readout channel for photon by photon signal processing, what provides better image quality and possibility of counting photons only within a given energy window. There are different trends in development of hybrid pixel detectors. One is to use nanometer or 3D technologies to include more complex functionality in single pixel cell together with good parameters of analog front-end electronics and high maximum pulse throughput per single channel. Another trend is targeted at building large area X-ray cameras which can be used by industry or novel scientific experiments mainly in material science, physics and biology. In both trends the problems to be solved are similar, however the priorities are a little bit different. This paper presents the main issues related to the development of semiconductor pixel detector systems on the examples of produced integrated circuits.

We present a prototype chip built in a 40 nm CMOS process for readout of a pixel detector. The prototype chip has a matrix of 18×24 pixels with a pixel pitch of 100 µm. It can operate in both: the single photon counting (SPC) mode and the C8P1 mode. In the SPC mode using the high gain setting the measured ENC is 84 e− rms (for the peaking time of 48 ns), the gain is 79.7 µV/e−, while the effective offset spread is 24 e− rms. In the C8P1 mode, the chip reconstructs full charge deposited in the detector, despite the charge sharing, and it points to a pixel with the largest charge deposition. The chip architecture and preliminary measurements are reported.

Hybrid pixel detectors working in a single photon counting mode are very attractive solutions for material science and medical X-ray imaging applications. Readout electronics of these detectors has to match the geometry of pixel detectors with an area of readout channel of 100 μm × 100 μm (or even less) and very small power consumption (a few tens of μW). New solutions of readout ASICs are going into directions of better spatial resolutions, higher data throughput and more advanced functionality. We report on the design and measurement results of two pixel prototype ASICs in nanometer technology and 3D technology which offer fast signal processing, low noise performance and advanced functionality per single readout pixel cell.

We report on the analysis, simulations and measurements of both noise and high-count rate performance of a single photon counting integrated circuit called UFXC32k designed for hybrid pixel detectors for various applications in X-ray imaging. The dimensions of the UFCX32k designed in CMOS 130 nm technology are 9.63 mm × 20.15 mm. The integrated circuit core is a matrix of 128 × 256 squared readout pixels with a pitch of 75 μm. Each readout pixel contains a charge sensitive amplifier (CSA), a shaper, two discriminators and two 14-bit ripple counters. The UFXC32k was bump-bonded to a silicon pixel detector with the thickness of 320 μm and characterized with the X-ray radiation source. The CSA feedback based on the Krummenacher circuit determines both the count rate performance and the noise of the readout front-end electronics. For the default setting of the CSA feedback, the measured front-end electronics dead time is 232 ns (paralyzable model) and the equivalent noise charge (ENC) is equal to 123 el. rms. For the high count rate setting of the CSA feedback, the dead time is only 101 ns and the ENC is equal to 163 el. rms.

We present the design and measurements of a novel 64 channel ASIC dedicated for recording and stimulation of neural network activity. Chip is designed in submicron CMOS 180nm technology, occupies 5×5 mm2 of silicon area, and consumes only 25 μW/channel. The low cut-off frequency can be tuned in the range 60 mHz-100 Hz while the mean high cut-off frequency is 4.7 kHz or 12 kHz. The recording channel voltage gain may be also changed. Mean measurement values show it may be either 139 V/V or 1100 V/V. The measured input referenced noise is 3.7 μV rms in band 100 Hz-12 kHz and 7.6 μV rms in band 3 Hz-12 kHz. For the input signals amplitude 1.5 mV, the THD is 1%. In order to satisfy requirements concerning spread of the main parameters of the multichannel system, each channel is equipped with the two corrections DAC's. These allow to obtain voltage gain equal to 139 V/V with the standard deviation std = 0.67 V/V, and low cut-off frequency equal to 60 mHz with the std = 30 mHz only. Each channel is equipped additionally with a stimulation circuits allowing to generate stimulation pulses in the 125 nA-512 μA current range with 8-bit resolution. All ASIC configurations are set thanks to on-chip digital register controlled by the on-chip LVDS receivers.

We report on the design of the VIPIC IC (Vertically Integrated Pixel Imaging Chip) designed for X-ray Photon Correlation Spectroscopy (XPCS) experiments by FNAL in collaboration with AGH-UST. The VIPIC chip is a prototype matrix with 64 × 64 pixels with 80 μm × 80 μm pixel size and consists of two layers: analog and digital. The single analog pixel cell consists of a charge sensitive amplifier, a shaper, a single current discriminator and trim DACs. The simulated gain is 52 μV/e−, the noise ENC det = 100 fF) and the peaking time t p < 250 ns. The power consumption is 25 μW/pixel in the analog part. The digital layer of the VIPIC integrated circuit is divided into 16 readout groups of pixels read out in parallel via separate serial ports with nominal frequency of the 100 MHz clock using the LVDS standard. The readout within each group is zero-suppressed. The sparsification scheme (addresses of hit pixels only) allows a dead-time free readout.

We present the design and simulation of the neural recording amplifier in the CMOS 180 nm technology. Amplifier is capable of recording signals from mHz range up to kHz range while rejecting large DC offset generated on the electrode-electrolyte interface. Its band may be control to span over all interesting biopotential signals (low cutoff frequency from 73 mHz to 125 Hz while the upper cutoff frequency from 1.85 kHz to 16.5 kHz). Due to its low input referred noise 4.5 muV (integrated from 1 mHz to 100 kHz), low power consumption 28 muW per one channel, small occupied area 0.094 mm2 and small spreads of its main parameters designed amplifier is a good candidate for multichannel neural recording system.

CdTe detectors are very good candidate for medical X-ray imaging applications, because of their relatively high atomic number and significant progress in their fabrication process during the last decade. For this reason we built a hybrid pixel detector based on CdTe sensor and the UFXC32k integrated circuit designed in CMOS 130 nm process and operating in a single photon counting mode. The core of the IC is the matrix of 128 × 256 square shaped pixels of 75 μm pitch. Each pixel contains a charge sensitive amplifier, a shaper, a discriminator, correction circuits and two 14-bit counters. The UFXC32k chip was bump-bonded to a pixel CdTe sensor and characterized using X-ray radiation. The measured equivalent noise charge is equal to 125 e-rms for the gain of 33 μV/e-. Thanks to a good quality of bump-bonding process we also managed to obtain a satisfactory X-ray radiograms.