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We introduce a new mode of oscillation in an LC-tank: an inverse class-F₂₃. In contrast to the conventional class-F oscillators, in which a high value of the real impedance (i.e., resistance) is presented to the third (in class-F₃) or/and to the second (in class-F₂/class-F₂₃) oscillator harmonics via an auxiliary resonance, here low resistive impedances (resembling a non-ideal short) are presented at both the second and third harmonics. This is made possible by tight magnetic coupling in the differential and common modes, respectively, afforded by a new compact 2:3 transformer. Being largely free from the harmonics in the voltage waveform and their possible deleterious phase shift effects on the flicker noise up-conversion, the phase noise performance in the flicker and thermal regions is further improved by narrowing the conduction angle. The 2:3 step-up transformer also provides a high passive gain to help with the startup in face of low supply. The switched-capacitor banks and cross-coupled transistor pair are carefully integrated under the transformer with a special arrangement of native (high-resistivity) substrate layer to mitigate their effect on the oscillation while reducing the area by 30%. The proposed digitally controlled oscillator (DCO) is implemented in 28-nm CMOS and achieves -95 dBc/Hz and -118 dBc/Hz at 100 kHz and 1 MHz offsets, respectively, while operating at a 0.3 V supply. The measured 1/f³ corner stays within 60 to 100 kHz over the 35% tuning range (TR) (from 2.02 to 2.87 GHz). This results in a figure-of-merit (FoM) with normalized TR (FoM $_{T}$ ) of -196 and -199 dB at 100 kHz and 1 MHz offsets, respectively, is a record in the space of ≤0.5 V and ≤1 mW.

Phase noisehas become the single most critical factor to be addressed in the design of modern communication systems. Facing the challenging requirements of 5G cellular communication, our paper describes a new theoretical framework to calculate the phase noise of LC oscillators, relying on easy to implement closed form solutions for phase noise calculations. Using closed form phase noise solutions enables oscillator designers to easily implement multiple phase noise calculation options for a number of oscillator circuits, which would be very difficult to implement with the existing mathematically complex phase noise theories. The analytic methods of our theory rely on modeling all real oscillators as having non-ideal or latent behaviors in addition to their primary nature for generating a carrier wave operating at a single frequency with a single amplitude. It is a cascade of these non-ideal transformation processes that produce non-ideal oscillator outputs containing the phase noise sidebands. Enhanced qualitative and quantitative insights into oscillator phase noise performances are achieved by using this approach. We validate our methods by comparing their results with phase noise simulations carried out for a sample CMOS LC voltage-controlled oscillator in 90 nm RFCMOS process using SpectreRF simulator. The results for the oscillator's output 1/f2 thermal phase noise, 1/f noise upconversion into 1/f3 phase noise and the 1/f3 corner frequency of phase noise spectrum using our theory yields −136 dBc/Hz at 10 MHz offset, −21.3 dBc/Hz at 1 kHz offset and 2.6 MHz respectively. The corresponding values obtained with SpectreRF simulation are −135.9 dBc/Hz, −23.4 dBc/Hz and 2.1 MHz. The carrier frequency is 5.4 GHz with output power of 9.78 dBm.

Analysis and design of a tetrahedral oscillator is presented. Expressions for the startup condition and oscillation frequency are derived. A phase noise analysis of thermal and flicker noise is carried out, using the impulse sensitivity function theory. The noise contribution of each type of transistor is studied, and the dominant and negligible cyclostationary noise sources are identified. There is good agreement among the theory and Spectre simulation. Design guidelines based on the analysis are provided.

In this article, a distributed-swing-boosting and harmonic-impedance-expanding multi-core oscillator is proposed to achieve low phase noise and high figure-of-merit (FoM), simultaneously. First, a distributed-coupling multi-core topology is introduced to reduce the chip area with no mode ambiguity. Then, the distributed-swing-boosting and harmonic-impedance-expanding structure is developed to boost the gate swing and square-like waveform of $V_{\text {DS}}$ . The common-mode (CM) resonances around the second harmonic and the differential-mode (DM) resonances around the third harmonic are utilized to suppress the flicker noise up-conversion and achieve harmonic shaping. Meanwhile, the dual-resonance response expands the high-impedance frequency ranges around the harmonics, and thus, the effect of harmonic shaping can be obtained over a wide frequency range. Fabricated in a 40-nm CMOS process, the oscillator measured exhibits low phase noise and high FoM simultaneously with a compact chip size. The minimum phase noise is −138.9 dBc/Hz at the 1-MHz offset, corresponding to an FoM of 195.1 dBc/Hz. The 1/ $f^{3}$ phase noise corner is 100–130 kHz over the 26.6% tuning range.

A novel active noise-shaping SAR ADC with on- chip digital DAC calibration is presented. To relax the design of the single op-amp used as an integrator, correlated double sampling (CDS) and correlated level shifting (CLS) were implemented. CDS minimizes the offset of the integrator and reduces the flicker noise, while CLS boosts the gain of the op-amp and reduces the power consumption. Also, a two-step incremental ADC based digital DAC calibration scheme was implemented to cancel the DAC mismatch errors and parasitics effects. The ADC was fabricated in 0.13 $\mu \text{m}$ CMOS technology. It achieved 85.1 dB DR, 82.6 dB SNDR and 90.9 dB SFDR within a 2 kHz signal bandwidth with an oversampling ratio OSR = 32. It consumes 40.8 $\mu \text{W}$ power using a 1.6 V power supply.

Methodological studies of spectral characteristics and statistical analysis of flicker noise are presented on the example of two data samples (2016–2017) on the X-ray nova A0620-00. The results obtained indicate the nature of flicker noise as aperiodic phenomenon in stellar atmospheres and in regions of interaction between stars in binary systems, including phenomena of a flare nature. We showed that flicker noise is described by distributions of non-negative random variables: gamma distribution and Weibull distribution, which makes it related to atmospheric processes in meteorology and geological processes (earthquakes). Modeling of these processes shows structural correspondence to real data (Hurst diagrams), and also indicates the presence of additional unaccounted for noise of a presumably Gaussian nature. The performed studies give recommendations to supplement the models of the light curves of binary astrophysical systems with the gamma distribution and the Weibull distribution.

This article presents a wide input-range delay chain based time amplifier (TA) and its application to a 6.5-GHz digital fractional- $N$ phase-locked loop (PLL). The TA includes a delay-averaging linearity enhancement technique and the PLL is based on an improved dual-mode ring oscillator (DMRO) delta-sigma ( $\Delta \Sigma $ ) frequency-to-digital converter (FDC). The TA mitigates contributions to the PLL’s phase noise from DMRO flicker noise, which would otherwise degrade the PLL’s in-band phase noise, and from $\Delta \Sigma $ FDC quantization error, which would otherwise degrade the PLL’s phase noise at high bandwidth settings. This paper also presents a delay-free asynchronous DMRO phase sampling scheme, and the first experimental demonstration of a recently-proposed $\Delta \Sigma $ FDC digital gain calibration technique. The TA-assisted PLL achieves a random jitter of 145 fsrms, a total jitter that ranges from 151 to 270 fsrms as a result of fractional spurs, and a worst-case fractional spur of −49 dBc without requiring nonlinearity calibration.

The oscillator phase noise is one of the key limitations in several fields of electronics. An electronic oscillator phase noise is usually described by the Leeson's equation. Since the latter is frequently misinterpreted and misused, a complete derivation of the Leeson's equation in modern form is given first. Second, effects of flicker noise and active-device bias are accounted for. Next the complete spectrum of an electronic oscillator is derived extending the result of the Leeson's equation into a Lorentzian spectral line. Finally the spectrum of more complex oscillators including delay lines is calculated, like opto-electronic oscillators.

This article proposes a quad-core millimeter-wave (mm-wave) oscillator using E-M mixed-coupling resonance boosting. The mixed-coupling resonator is introduced to generate four reconfigurable resonances. The magnetic coupling and electric coupling are achieved by the symmetrically coupled transformer and coupling capacitor, respectively. A 2-D mode switch array is introduced to couple the quad-core and achieve the quad-mode switching without degrading the performance of the selected mode. Therefore, the reduction of phase noise and the extension of tuning range are achieved simultaneously. Meanwhile, the digitally controlled tail-resistor array is used to optimize the flicker noise up-conversion in wideband. Prototyped in 40-nm CMOS, the proposed oscillator exhibits a 73.2% tuning range from 18.6 to 40.1 GHz. The best phase noise at 1-MHz offset is −108.5 dBc/Hz, corresponding to an figure-of-merit (FoM) of 184.4 dBc/Hz and FoMT of 201.7 dBc/Hz. The variation range of FoM over the whole frequency range is 3 dB. The 1/ $f^{3}$ phase noise corner is 220–620 kHz.

High-fidelity photodetection enables the transfer of the low noise inherent to optical oscillators to the microwave domain. However, when photodetecting optical signals of the highest timing stability, photodiode flicker (1/f) noise can dominate the resulting timing jitter at timescales longer than ∼1 ms. With the goal of improving femtosecond-level timing fidelity when transferring from the optical to microwave domain, we vary the duty cycle of a train of optical pulses and show that the photodetector flicker phase noise on a photonically generated 1 GHz microwave signal can be reduced by ∼10 dB under ultrashort pulse illumination, reaching as low as −140/f dBc/Hz. In addition, a strong correlation between amplitude and phase flicker noise is found, implying a single baseband noise source can modulate both quadratures of the microwave carrier. These findings expand the limits of the ultimate timing stability that can be transferred from optics to electronics.

A rotary traveling-wave oscillator (RTWO) has an ability to generate multiple phases at millimeter-wave (mmW) frequencies while achieving low phase noise (PN). Unfortunately, due to the practically unavoidable transmission line (TL) dispersion, which causes the higher-order harmonics to travel faster than the fundamental, RTWOs suffer from flicker noise upconversion. In this article, we propose a “distributed stubs” technique to mitigate this mechanism in which tuning capacitors placed on the TL stubs away from the maintaining amplifiers will slow down the travel speed of higher-order harmonics relative to the fundamental, thus lowering the phase shifts due to the TL dispersion. We further provide a comprehensive analysis of the flicker noise upconversion mechanism due to the TL dispersion. The proposed 26.2–30-GHz RTWO is implemented in 22-nm fully depleted silicon-on-insulator (FD-SOI) CMOS with eight differential phases. At 30 GHz, it achieves PN of −107.6 and −128.9 dBc/Hz at 1- and 10-MHz offsets, respectively. This translates into figures-of-merit (FoMs) of 184.2 and 185.4 dB, respectively, for a single phase. The proposed architecture consumes 20 mW from 0.8-V supply. It achieves a flicker PN corner of 180 kHz, which is an order-of-magnitude better than currently achievable by state-of-the-art mmW RTWOs.

This work presents a power-efficient and noise-efficient amplifier for ECG recordings. To improve power efficiency, all the transistors in the proposed amplifier is designed in sub-threshold region which gives high g $$_m$$ /I $$_D$$ ratio. To improve noise efficiency, inverter-based differential input stage is used in this proposed operational transconductance amplifier as it reduces noise by a factor of $$\sqrt{2}$$ when compared to it’s non-inverter based counterpart. In order to decrease flicker noise, large transistors are used in the input stage. Class A–B structure is used in the output stage for achieving high g $$_m$$ /I $$_D$$ ratio and for large output swing range. In 180 nm process the amplifier consumes 477 nW DC power from 1.8 V supply which indicates 7.5% decrease in power consumption when compared to recently reported papers. This amplifier achieves a noise efficiency of 2.68. Common mode rejection ratio and power supply rejection ratio is estimated as 98.5 dB and 104.5 dB respectively.

We report the results of theoretical and experimental studies of noise in a delay-line optoelectronic microwave oscillator with optical gain. The effect of various noise sources on the parameters of an optoelectronic microwave oscillator is considered, and, in addition to the noise of its individual components, several linear and nonlinear mechanisms for converting optical carrier noise into microwave signal noise are taken into account. It is shown that, due to the nonlinearity of the energy characteristics of high-power microwave photodiodes in an optoelectronic generator, the low-frequency components of the laser relative intensity noise are converted into microwave signal noise, as a result of which sources of correlated amplitude and phase noise appear in the oscillator loop.

Drain-extended MOSFET (DEMOS) with halo implant induced laterally asymmetric channel doping shows anomalous characteristics across bias and temperature that cannot be captured by existing models. The transconductance ( ${g}_{m}$ ) maxima in the linear region is found to be not only a function of the peak mobility but also the halo doping density. In the saturation region, the ${g}_{m}$ characteristics show a nonmonotonic “hump” induced by the halo-region/channel-region junction barrier. Another key care-about for analog design - the drain current ( ${I}_{D}$ ) mismatch, also exhibits unique characteristics with excess mismatch in the weak-inversion (WI) region, in particular at low temperature. In addition, the anomalous flicker noise ( ${1}/{f}$ noise) trends in the presence of high-trap density in the halo region of halo-implanted DEMOS are also discussed. In this work, we propose an analytical model based on the equivalent conductance and impedance field theory to capture these effects. The proposed model is in good agreement with measurements and numerical device simulations using technology computer-aided design (TCAD) of DEMOS across a different oxide thickness, geometry, bias, and temperature.

In this paper, we experimentally demonstrate the impacts of laboratory vibrations and laser flicker noise on digital holography (DH). Specifically, we measure both the vibration efficiency and the coherence efficiency of our DH system at various focal-plane array integration times and path-length differences between the signal and reference. These efficiencies, in practice, contribute to the overall mixing efficiency, which is a measure for how well the detected signal and reference interfere. The results show that when the integration time is ≤1ms, the laboratory vibrations are negligible with a vibration efficiency of 100%; however, when the integration time equals 100 ms, the laboratory vibrations lead to a 94% vibration efficiency. In addition, the results show that the effective coherence length of the master-oscillator (MO) laser increases by 280% when the integration time decreases from 100ms to 100 $\mu \text{s}$ . To account for this outcome, we present a model of the coherence efficiency based on the frequency noise of the MO laser. The model fit to the DH data then shows that the frequency of the MO laser is flicker-noise dominated. As a result, decreasing the integration time improves the overall mixing efficiency because of high-pass filtering in both the vibration efficiency and the coherence efficiency. Based on previous published efforts, these results have direct ties to the achievable signal-to-noise ratio of a DH system.

A harmonic-tuned (HT) voltage-controlled oscillator in a 65-nm CMOS process is demonstrated in this letter. The oscillation frequency and harmonics are tuned independently by two separated high- $Q$ resonators. A novel F23 inductor–capacitor resonator resonating at the second and third harmonics simultaneously is introduced. The proposed F23 inductor has a high-quality factor of 15 and 24 in common-mode (CM) and differential-mode (DM), respectively. The simulation results show that a 4.3-dB phase noise (PN) improvement is achieved in the thermal noise region due to the high- $Q$ HT method. Meanwhile, less harmonic currents are injected into the fundamental resonator due to the source-degeneration principle, hence decreasing the Groszkowski effect and suppressing the flicker noise. The measured PN is −117.5 dBc/Hz at the 1-MHz offset, and the tuning range is 12% from 6.80 to 7.66 GHz. The flicker noise corner is around 220 kHz and the figure-of-merit is 187.2 dBc/Hz. The power consumption is 5 mW under a 0.55-V supply.

This study presents a new low-power and low-phase noise Colpitts quadrature voltage-controlled oscillator (QVCO). The proposed QVCO contains two differential Colpitts voltage-controlled oscillators (VCOs) that use gain-boosting technique to enhance the negative transconductance and relax start-up condition. Both switching and tail transistors are configured in class-C to improve impulse sensitivity function and phase noise performance of the circuit via better noise modulation function. In addition, flicker noise would be reduced because of the switched-biasing mechanism of tail transistors. Phase noise analysis shows that changing the bias voltage of switching as well as tail transistors can improve the phase noise performance of the core VCO with overlap reduction of the transistors active time. Consequently, due to no extra noisy elements for coupling and class-C biasing of all transistors, low-phase noise quadrature signals are generated. To verify the performance of the proposed technique, post-layout simulation is performed in Taiwan Semiconductor Manufacturing Company (TSMC) of 0.18 μm Radio Frequency-Complementary Metal-Oxide- Semiconductor (RF-CMOS) process at a supply voltage of 1.2 V. Post-layout simulation results show that the phase noise of the proposed QVCO is −120.6 dBc/Hz at 1 MHz offset from 5.73 GHz operation frequency. The total power consumption of the QVCO is 3.1 mW and the tuning range is from 5 to 5.73 GHz.

We present design considerations for CT $\!\Delta \!\Sigma $ Ms that attempt to achieve high resolution (16+ bits) over a wide bandwidth (>200 kHz), resulting in a low in-band noise spectral density. The main challenges in such designs are parasitic resistance in the reference path, inter-symbol interference (ISI) in the feedback-digital-to-analog converter (DAC) waveform, and flicker noise of the input operational transconductance amplifier (OTA). We introduce the virtual-ground-switched resistor DAC as a way to achieve low distortion by addressing parasitic resistance in the reference path and reducing the effects of ISI. Flicker noise is reduced by chopping the first stage of the input OTA. Chopping artifacts and clock jitter sensitivity are reduced by using a three-stage OTA and finite impulse response (FIR) feedback. These techniques are applied to the design of a 250 kHz bandwidth CT $\!\Delta \!\Sigma \text{M}$ targeting 108 dB signal-to-noise-and-distortion-ratio (SNDR) in a 180 nm CMOS process. The fabricated prototype, which operates at 32 MS/s, achieves 105.3/108.1 dB SNDR/signal-to-noise-ratio (SNR) and consumes 24 mW. The Schreier SNDR figure of merit (FoM) is 175.5 dB.

This paper presents a K/Ka-band voltage biased differential LC-VCO in 22nm FD-SOI achieving a 1/f 3 corner below 18 kHz and a figure-of-merit (FOM) at 1 MHz offset frequency of 188~190 dBc/Hz over the tuning range. Thanks to the flicker noise filtering technique, flicker noise upconversion can be suppressed significantly without degrading the phase noise (PN) in the 1/f 2 region. The difference in connection of the switched-capacitor bank (SCB) over the VCO tuning range is taken into account in our analysis of flicker noise filtering. The VCO uses differential source degeneration with a self-coupled inductor that is used for layout compactness and common-mode (CM) resonance manipulation. To obtain a low 1/f 3 corner over the tuning range, a common centroid layout technique is used for the SCB. The post-layout simulation shows that the 1/f 3 corner is well below 50 kHz over the tuning range in different process corners. The PN@1 MHz and PN@100 kHz are -110.2 dBc/Hz and -89.9 dBc/Hz, respectively, at the center of the tuning range with a power consumption of 8.8 mW.

This article presents a near-field dielectric plethysmography (DPG) heart-rate sensor for low-power operation. By interrogating the contracting and expanding blood vessels with gigahertz-frequency fringing electric fields from the on-board coplanar waveguide (CPW) transmission line, pulsing heart-rate signals are detected using a phase-sensitive interface circuit through changing permittivity at the fingertip. Signal analysis, frequency response measurements, and variability studies are provided to demonstrate the robustness of DPG for heart-rate detection. The readout circuit employs a highly digital time-based edge sampling with the rail-to-rail signaling and double-integration chopper stabilization technique to maximize the electronics sensitivity and to minimize the flicker noise. Implemented in the 0.18- $\mu \text{m}$ CMOS technology, the phase-sensitive readout circuit exhibits a limit of detection of 0.0033° and consumes 20.1 $\mu \text{W}$ under a sampling and duty-cycling rate of 100 Hz and 0.0256%, respectively. With the integration of CPW sensor in a low-cost FR-4 printed-circuit board (PCB), the 1.8-GHz DPG heart-rate sensor achieves an rms inaccuracy of 1.64 bpm.

This article presents a discrete-time second-order $\Delta \Sigma $ modulator for the audio applications. In this modulator, a novel dynamic amplifier is proposed to realize the switched-capacitor (SC) integrators. To eliminate the common-mode (CM) voltage drop in a closed-loop dynamic amplifier during the integration phase, without the use of additional load capacitance, the reset method for the amplifier is modified. Two auxiliary branches are introduced to enhance the settling speed of the integrator. Two different flicker noise reduction techniques (FNRTs) are developed to improve the signal-to-noise-and-distortion ratio (SNDR) (about 2 dB in the audio bandwidth). The prototype modulator is fabricated in 65-nm CMOS technology with a 0.12-mm2 core area, which achieves a dynamic range (DR) of 91 dB and a peak SNDR of 89.6 dB in the 24-kHz signal bandwidth. It consumes only 49- $\mu \text{W}$ power from a 0.8-V supply, translating into a Schreier figure of merit (FoM) of 176.5 dB.

Flicker noise contributed by active mixers usually compromises the overall sensitivity level of direct-conversion receivers (DCRs). In this article, a qualitative quasi-analytical model has been developed to in-depth explain the flicker noise mechanism existing in the switched-gm active mixer in which an improved current source switch is presented for high mixer common-mode rejection ratio (MCMRR). The built model simply explains how frequency translations take place within the mixer. Compact equations are derived to estimate the flicker noise contribution of individual stages at the output. Simulations validate the accuracy of the predictions, and the dependence of flicker noise on local oscillator (LO) slope ratio, period, and other circuit parameters. The high-frequency limitation of the mixer is further estimated by investigating into the tail parasitic capacitance charging and discharging behavior. Furthermore, a switched-gm pMOS mixer prototype with low flicker noise is implemented in a 0.18- $\mu \text{m}$ CMOS process. It operates at an RF input frequency of 1 GHz and provides a maximal conversion gain of 12.9 dB and an NF of 11.4 dB while a flicker noise corner of 220 kHz and an IIP3 of 3.6 dBm are measured, respectively. The mixer core only consumes 3.3 mW from a 1.8 V supply.

Frequency modulation technology has been widely used in many fields to get rid of the limitation of the 1/f flicker noise. However, the residual amplitude modulation (RAM) seriously deteriorates the detection accuracy of frequency modulation technology. Especially, for fiber electro-optic modulator (f-EOM), the RAM cannot be minimized by the conventional technique commonly used for free-space EOM such as careful mechanical adjustment or using a wedged crystal EOM. This can limit the use of f-EOM in high-performance detection techniques. In an ultra-stable laser system, the existence of the RAM has become one of the important factors limiting the frequency stability. This paper develops a dual-loop active feedback servo system to minimize the RAM. The voltage and temperature dependence of the EOM are measured to design a suitable active RAM reduction controller. To verify its ability, the active RAM reduction system is placed in an ultra-stable laser system for testing. The RAM noise is suppressed to less than 1 ppm and the corresponding laser frequency stability is 1×10−16. The RAM-reduced frequency stabilization is lower than the thermal noise limit of the reference cavity, so the RAM will not be the main factor affecting the laser frequency stability in the ultra-stable laser system.

Flicker noise causes decoherence in Josephson junction-based superconducting qubits, thus limiting their practical potential as building blocks for quantum computers. This is due to limited length and complexity of executable algorithms, and increased dependency on error-correcting measures. Therefore, identifying and subsiding the atomic sources of flicker noise are of great importance to the development of this technology. We developed a method that combines ab initio DFT calculations and quantum dynamics to model charge transport across a Josephson junction, by which it is possible to more accurately assess different defects as sources of flicker noise. We demonstrate the use of our method in an investigation of various atomic defects, including vacancies, trapping, and substitutions, in an Al|Al2O3|Al Josephson junction. This demonstration both reveals weaknesses in previous attempts to pinpoint the atomic sources of flicker noise and highlights new candidates.

In this paper, for the high impedance marine electric field sensor (MEFS), a marine electric field signal amplification circuit (MEFSAC) with ultra low noise and high input impedance is designed, and the noise analysis of the circuit is carried out. In order to achieve the ultra low noise performance of the circuit, the chopper modulation technology is introuduced to reduce the flicker noise generated by the circuit. The AC amplifier stage with instrumentation amplifier structure is implemented to achieve the coupling of the circuit with the sensor to reduce coupling noise, and the low-pass filter stage with a cut-off frequency of 100Hz is designed to filter out the high-frequency signal generated by the circuit. The noise model of the MEFSAC is established, and the noise of the MEFSAC is analyzed theoretically and the simulation is verified. The gain of the MEFSAC is 60dB, and the background noise of the MEFSAC is 1.87nV/rt(Hz). Through the analysis of circuit noise model, it provides a better method for seeking circuit noise suppression.

Surface acoustic wave (SAW) sensors for the detection of magnetic fields are currently being studied scientifically in many ways, especially since both their sensitivity as well as their detectivity could be significantly improved by the utilization of shear horizontal surface acoustic waves, i.e., Love waves, instead of Rayleigh waves. By now, low-frequency limits of detection (LOD) below 100 pT/Hz can be achieved. However, the LOD can only be further improved by gaining a deep understanding of the existing sensor-intrinsic noise sources and their impact on the sensor’s overall performance. This paper reports on a comprehensive study of the inherent noise of SAW delay line magnetic field sensors. In addition to the noise, however, the sensitivity is of importance, since both quantities are equally important for the LOD. Following the necessary explanations of the electrical and magnetic sensor properties, a further focus is on the losses within the sensor, since these are closely linked to the noise. The considered parameters are in particular the ambient magnetic bias field and the input power of the sensor. Depending on the sensor’s operating point, various noise mechanisms contribute to f0 white phase noise, f−1 flicker phase noise, and f−2 random walk of phase. Flicker phase noise due to magnetic hysteresis losses, i.e. random fluctuations of the magnetization, is usually dominant under typical operating conditions. Noise characteristics are related to the overall magnetic and magnetic domain behavior. Both calculations and measurements show that the LOD cannot be further improved by increasing the sensitivity. Instead, the losses occurring in the magnetic material need to be decreased.

This brief aims to intuitively explain and numeri- cally verify the observed phenomenon of flicker noise reduction in oscillators of reduced conduction angle (i.e., in class-C), which has been presented in literature but never properly explained. The flicker phase noise in a voltage-biased oscillator capable of operating in class-B and class-C is compared and numerically verified using a commercial simulation model of TSMC 28-nm CMOS. We illustrate how narrowing the conduction angle can suppress the 1/f noise up-conversion by decreasing 1/f noise exposure to the asymmetric rising and falling edges of oscillation waveform. The effects of implicit common-mode tank in the class- C operation is also discussed. We further clarify ambiguities among several simulation methods of impulse sensitivity function (ISF) based on periodic small-signal analysis (PAC or PXF), which is a key tool in understanding the flicker noise up- conversion. A clearer ISF simulation method based on positive sidebands of PXF is proposed. European Commission European Commission - Seventh Framework Programme (FP7) Science Foundation Ireland Update citation details during checkdate report - AC 2019-05-11 JG: PDF updated at author's request

In this paper, we examine the origins of bias instability in three-axis, mode-matched MEMS gyroscopes. Reducing this drift phenomenon is crucial for highly accurate navigation in applications, such as automated driving or indoor localization. We show that for a typical MEMS gyroscope, bias instability noise becomes the dominant orientation error component after less than 10 s of integration time. A model-based approach summarizing the most common sources of zero-rate offset is combined with a detailed experimental analysis. We find naturally occurring flicker noise acting on the frequency tuning electrodes to be the dominant source of bias instability for the in-plane axis. By controlling the frequency tuning state, we establish an unprecedented value for bias instability of an automotive-type MEMS gyroscope of lower than 0.1 dph—more than a factor 10 improvement from its performance in ordinary operation. Furthermore, we analyze the so far sparsely studied effect of scale-factor instability, which is an increase of drift that scales with applied angular rate. This phenomenon is particularly important for applications, where high angular rates are common, such as dead-reckoning with smart-phones. As out-of-plane MEMS gyroscopes are significantly more challenging to manufacture, their performance has been studied much less. The out-of-plane axes in this paper are shown to exhibit a complex composition of bias instability sources with a total level as low as 0.7 dph. The presented gyroscopes were furthermore designed for ultra-low white noise. The angle random walk (ARW) is lower than 2.5 md/s/rtHz in all three axes. [2018-0165]

1/ ${f}$ noise is characterized on thick and thin-gate oxide-based FinFETs for different channel lengths. The devices exhibit gate bias dependence in 1/ ${f}$ noise even in the weak-inversion region of operation which cannot be explained by the existing flicker noise model. We attribute this phenomenon to the non-uniform oxide-trap distribution in energy or space. Based on our characterization results for n- and p-channel FinFETs, we have improved the BSIM-CMG industry standard compact model for the FinFETs. The improved model is able to capture the 1/ ${f}$ noise behavior over a wide range of biases, channel lengths, fin numbers, and number of fingers.

A dual chopper amplifier (DCA) signal conditioning circuit with ultra-low power consumption is presented for microelectromechanical systems transducers. In the first stage, a low voltage high current amplifier is implemented, which improves the power consumption and noise floor. The second stage is composed of two parallel paths that improve SNR and provide two gain settings. To mitigate flicker noise, the amplifiers are chopped at two different frequencies, also providing an additional degree of freedom to the design. The circuit is designed in a 0.13 $\mu \text{m}$ CMOS technology with 0.7 and 1.2 V supplies. The power consumption is of 2.66 $\mu \text{W}$ at the 0.7 V supply and 3.26 $\mu \text{W}$ at the 1.2 V supply. For a 1.6 mV input, in single path mode, the DCA has a gain of 34 dB, a bandwidth of 4 kHz and achieves an SNR of 89.06 dB in the frequency range of 0.5–4 kHz. In dual path mode, the DCA has a gain of 38 dB, a bandwidth of 3 kHz and achieves an SNR of 92.85 dB in the frequency range of 0.5–4 kHz. The effect of the chopper at the second amplifier in the single path and dual path modes is detailed.

In this paper, we propose a 60-GHz fractional- ${N}$ digital frequency synthesizer aimed at reducing its phase noise (PN) at both the flicker ( $1/\!f^{3}$ ) and thermal ( $1/\!f^{2}$ ) regions while minimizing its power consumption. The digitally controlled oscillator (DCO) fundamentally resonates at 20 GHz and co-generates a strong third harmonic at 60 GHz which is extracted to the output while canceling the 20-GHz fundamental. The latter component is fed back to the frequency dividers in an all-digital phase-locked loop for phase detection, which comprises a pair of digital-to-time and time-to-digital converters with $\Sigma \Delta $ dithering to attenuate fractional spurs. The mechanism of flicker noise upconversion to $1/\!f^{3}$ PN in the DCO is investigated, and a reduction technique is proposed. The 28-nm CMOS prototype achieves 213–277-fs rms jitter in the 57.5–67.2-GHz tuning range while consuming only 40 mW. The DCO flicker PN corner is record low at 300–400 kHz.

The phase noise of surface acoustic wave resonators is explored by a passive measurement system based on the carrier suppression technique. The measurements are focused on 2.44-GHz quartz crystal resonators. These resonators are characterized in terms of motional parameters. The power dissipated through the resonators is around $500~\mu \text{W}$ . The second-order frequency-temperature coefficient of the resonators has been measured to be around −0.038 ppm/°C2 that corresponds to a classical ST cut. The resonator conditioning is presented. The measured noise exhibits a 1/ $f$ frequency fluctuation behavior. The short-term stability (flicker floor) is given in terms of Allan standard deviation. The order of magnitude is around $2\times 10^{\mathbf {-10}}$ . Additional measurements are given for resonators at 433 and 915 MHz in order to compare them. The results are presented according to the intrinsic quality factor of the resonators and compared to the previous works done in the past by T. Parker. These additional data provide valuable information on the dependence of the flicker noise levels on resonator frequency.

A chopping technique in a continuous time K-delta-1-sigma modulator (KD1S) is reported in this paper. It is shown that the presence of the inherent path filter in the proposed technique can significantly improve the performance of the modulator by minimizing the aliased quantization noise. Also reported are how the selection of chopping frequency and its relation to sampling frequency and the trade-offs. To support the theory, a first order K-delta-1-sigma topology was designed in a 180nm CMOS process. Simulations are used to illustrate the validity of the results. The modulator works at a sampling frequency of 1 MHz with an oversampling ratio of 256. It consumes an average current of 61.18 µA from 1.8 V supply. The simulation result shows that there is more than 25dB improvement in the Signal-to-Noise Ratio (SNR) of the KD1S, when chopped at the right frequency.

This paper presents a D-band 2-channel dual downconversion receiver front-end with a sliding IF architecture in 22nm FDSOI process. A fully-differential D-band low-noise amplifier (LNA) followed by an active double-balanced mixer is first used and down-converts the 137–157 GHz RF signal to an intermediate frequency (IF) of 31–40 GHz. The IF signal is split into I and Q channels and is down-converted to zero-IF output I/Q signals using a passive mixer for low 1/f noise. A x6 LO (17.5 GHz to 35 GHz and to 105 GHz) chain is included on the chip and provides the required LO for both mixers. The receiver achieves a measured peak gain of 27-30 dB, a noise figure of 9-10.5 dB at 136–154 GHz, a simulated output flicker noise corner frequency of 25 kHz and consumes 395 mW for both channels and the LO chain. The measured input P1dB is −29 dBm resulting in a high SNR for wide bandwidth signals. A measured EVM of 4.3-4.8% was achieved at 1–2 Gbaud for 16-QAM and 64-QAM waveforms. To the authors' knowledge, this work presents the first D-band CMOS I/Q receiver with application areas in dual-polarized receivers for point-to-point systems and digital beamforming MIMO arrays.

In this paper, a high gain 77-GHz receiver with a low noise figure (NF) was designed and implemented in a 40-nm CMOS process. With the purpose of making better use of active devices, an extra inductor, Ld, is adopted in the new neutralization technique. The three-stage differential low noise amplifier (LNA) using the proposed technique improves the voltage gain and reduces the NF. The receiver design utilizes an active double-balanced Gilbert mixer with a transformer coupling network between the transconductance stage and the switch stage. The flicker noise contribution from the switch MOS transistors is largely reduced due to the low DC current of the switch pairs. The LO signal is provided by an on-chip fundamental voltage-controlled oscillator (VCO) with a tuning range from 70.5 to 78.1 GHz. A conversion gain of 32 dB and a NF of 11.86 dB are achieved at 77 GHz by the designed receiver. The LNA as well as the mixer consume a total DC power of 33.2 mW and occupy a core size of 1 × 0.38 mm2.

Fundamental limits of fiber link are set by non-reciprocal effects that violate the hypothesis of equality between forward and backward path. Non-reciprocal noise arises technically from the set-up asymmetry, and fundamentally by the Sagnac effect when the fiber link encloses a non-zero area. As a pre-requisite for observation of Sagnac effect in fiber links, we present a study on phase noise and frequency stability contributions affecting coherent optical frequency transfer in bi-directional fiber links. Both technical and fundamental limitations of Two-Way optical frequency transfer are discussed. Our model predicts and our experiments substantially verify that the dominant noise mechanism at low Fourier frequencies is the polarization asymmetry induced by the temperature and relative humidity variations impacted on fiber links. The flicker noise floor due to the non-reciprocal noise arising from polarization mode dispersion is evidenced for the first time. We perform a post-processing approach which enables us to remove this polarization noise, improve the long-term stability and remove a frequency bias. We evaluate the uncertainty contributions of all the effects discussed for our 50 km spooled fiber link, dominated by its non-reciprocal noise induced by polarization mode dispersion with uncertainty of 1.9( ± 0.8)( ± 1.2) × 10−20. After correction, the linear drift of the residual phase is as low as 27 yoctosecond/s, leading to an uncertainty of the frequency transfer of 2.6 ( ± 39) × 10−22, confirming its potential for searching for more fundamental effects such as Sagnac effect or transient frequency variation due to dark matter.

This paper presents a 0.8-mW 0.2-mm2 9-level second-order single-loop SC Delta-Sigma modulator (Δ∑M) ADC in 1.8-V 0.18-µm CMOS technology for low-power high-resolution sensing applications. The Δ∑M circuit features 94.6-dB peak SNDR in 50-kHz bandwidth and 103.5 dB SFDR up to -1 dB FS input for 2-Vpp differential full scale. The proposed built-in CDS flicker noise cancellation allows a net improvement of 10 dB FOM S . The bootstrapping-free CMOS circuits incorporate variable-mirror Class-AB switched OpAmps and a 10μW resistor-less flash quantizer. The obtained 172.6-dB FOM S is competitive within the state-of-art high-resolution (SNDR > 90 dB) and generalpurpose (bandwidth > 20 kHz) SC ASM ADCs.

An analytical model of flicker noise (also called 1/f or low frequency noise) for the drift region is developed to formulate a 1/f model for high voltage MOSFETs using the sub-circuit approach in this work. For halo doped drain extended MOSFET (DEMOS), the contribution factors of halo, channel and drift regions are obtained to capture anomalous behavior of 1/f noise. Similar to Halo doped DEMOS, for LDMOS, the contribution factors for channel and the drift region are obtained to capture the S ID for different drain biases and channel lengths. The proposed model is validated with measurement data of 50V LDMOS and DEMOS.

In this paper, a 24 GHz direct conversion receiver (DCR) for frequency-modulated continuous-wave (FMCW) ranging radar based on low flicker noise mixer in 90 nm silicon-on-insulator (SOI) CMOS technology is presented. A low-noise and low-power low-noise-amplifier (LNA) adopting simultaneous noise and input matching (SNIM) method is designed. Neutralized technology and boost inductor are introduced to improve performance. The measurement results of standalone LNA show that the peak gain is 17.2 dB at 23.8 GHz and the −3 dB bandwidth is around 2.2 GHz from 22.8 GHz to 25 GHz. The LNA achieves an average 3 dB NF within the 24 GHz band. A current-bleeding mixer is used to lower noise and the factors influencing flicker noise have been discussed. Proper element values and local oscillator (LO) power have been chosen to make the mixer low-noise. Measurement results illustrate that the receiver exhibits 20.3 dB peak gain, 7 dB SSB noise figure (NF) and −22 dBm IP1dB. Flicker noise of the mixer and the receiver are measured respectively and the noise knee-point of receiver is observed 60 kHz. The receiver consumes only 16 mW with chip area of 0.65 mm2 including pads. The results demonstrate that the proposed receiver can be a promising candidate for FMCW ranging radar.

Bio-impedance (BioZ) is an important physiological parameter in wearable healthcare sensing. Besides the inherent cardiac and respiratory information, BioZ can be also used for other emerging applications such as non-invasive blood status sensing [1]. A conventiona14-e1ectrode (4E) setup eliminates the effect of electrode-tissue impedance (ETI) at the expense of user comfort, system complexity, and cost. On the other hand, a 2-electrode (2E) setup avoids short-falls of 4E but can only capture relative changes of Bi0Z instead of its absolute value. In addition, a readout front-end (RFE) with wide dynamic range (DR) and high signal-to-noise ratio (SNR) is needed to deal with small BioZ variation (0.1$\sim10\Omega$) as well as large baseline resistance (>10k$\Omega$). A conventional RFE architecture employing an instrumentation amplifier (IA) and ADC has to trade-off between resolution, DR and noise [2, 3]. Although flicker noise in the current generator (CG) is mitigated through dynamic element matching (DEM) [2], the reference current (IREF) noise issue remains unaddressed. In [5], digital-assisted baseline cancellation and IREF correlated noise cancellation are proposed, which help eliminate IREF noise and input-dependent noise [4] due to the large signal in the current-balance instrumentation amplifier (CBIA). Nevertheless, larger noise is still observed due to the finite residual current $(I_{res})$ from the baseline cancellation.

In this work, a multi-mode radar transceiver supporting pulse, FMCW and CW modes was designed as an integrated circuit. The radars mainly detect the targets move by using the Doppler frequency which is significantly affected by flicker noise of the receiver from several Hz to several kHz. Due to this flicker noise, the long-range detection performance of the radars is greatly reduced, and the accuracy of range to the target and velocity is also deteriorated. Therefore, we propose a transmitter that suppresses LO leakage in consideration of long-range detection, target distance, velocity, and noise figure. We also propose a receiver structure that suppresses DC offset due to image signal and LO leakage. The design was conducted with TSMC 65 nm CMOS process, and the designed and fabricated circuit consumes a current of 265 mA at 1.2 V supply voltage. The proposed transmitter confirms the LO leakage suppression of 37 dB at 24 GHz. The proposed receiver improves the noise figure by about 20 dB at 100 Hz by applying a double conversion architecture and an image rejection, and it illustrates a DC rejection of 30 dB. Afterwards, the operation of the pulse, FMCW, and CW modes of the designed radar in integrated circuit was confirmed through experiment using a test PCB.

The article refers to the field of research of noise fluctuations or flicker noise in electronic amplifiers and is devoted to the exact definition of the magnitude and shape of the spectral density of flicker-noise. The 1/f approximation of flicker noise is analyzed and the problem of its non-constructiveness in analyzing the noise characteristics of electronic amplifiers is shown. To eliminate this problem, the mechanism of physical formation of the envelope, a form of spectral density flicker-noise is defined. The physics of flicker-noise is detailed by accurate definition of the place of its formation. An accurate definition of the maximum difference of the amplifier flickernoise on the flat section of noise characteristics is given, using an explanation of the physics of flicker noise. The mechanism and conditions of the exponential increase of flicker noise and its subsequent exponential desire for maximum magnitude are explained. A simple physical approximation is given to determine the processes of forming the envelope form of the spectral density of flickernoise. The physical understanding of the formation of spectral density of flicker-noise tension in the internal structure of the transistor with the participation of external circuits of the amplifier electrical circuit is detailed. The results of the study will help developers to solve many problems of building electronic devices and optimizing their characteristics at a qualitatively new level.

The paper presents a generalization of the Groszkowski’s result in differential oscillators, providing novel equations to describe the oscillation frequency dependence on the harmonic content. The effect of the common-mode oscillation is rigorously included. Moreover, an additional term, arising from the dependence of the transistor current on the drain voltage, which is dominant any time ohmic operation occurs, is disclosed here for the first time. This framework is applied to Van der Pol oscillators, both nMOS and CMOS, designed in a 28-nm bulk CMOS technology. The results correctly match the oscillation frequency dependence derived from detailed circuit simulations. The analysis shows that, when even harmonics are relevant, the classical Groszkowski’s result is not able to account for close-in phase noise performance. The novel theoretical framework fully justifies, instead, the simulation results and sheds new light on the flicker noise up-conversion mechanisms in the considered oscillator structures.