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An energy-efficient fast start-up method for crystal oscillators is presented, which enables aggressive duty-cycled operation of IoT radios to minimize overall power consumption. A digitally controlled crystal oscillator using the proposed start-up technique in 90-nm CMOS is presented. Thanks to the dynamically adjusted load, the negative resistance is boosted, achieving a $13\times $ start-up time reduction and an overall power of $95\mu \text{W}$ for a 24-MHz crystal oscillator at 1 V. A fully autonomous feedback loop detects the oscillators envelop and adjusts the load capacitance at start-up. Thanks to the low-power start-up circuits, both the start-up time and the start-up energy are reduced. In addition, the robustness and versatility of the proposed method is verified by measuring quartz crystals with different frequencies and quality factors, as well as measuring against temperature, supply voltage, and load capacitance variations. [ABSTRACT FROM AUTHOR]

This paper introduces an ultra-low power 1.7-2.7-GHz fractional-N sub-sampling digital PLL (SS-DPLL) for Internet-of-Things (IoT) applications targeting compliance with Bluetooth Low Energy (BLE) and IEEE802.15.4 standards. A snapshot time-to-digital converter (TDC) acts as a digital sub-sampler featuring an increased out-of-range gain and without any assistance from the traditional counting of DCO edges, thus further reducing power consumption. With a proposed DCO-divider phase rotation in the feedback path, the impact of the digital-to-time converter’s (DTC’s) non-linearity on the PLL is reduced and improves fractional spurs by at least 8 dB across BLE channels. Moreover, a “variable-preconditioned LMS” calibration algorithm is introduced to dynamically correct the DTC gain error with fractional frequency control word (FCW) down to 1/16384. Fabricated in 40 nm CMOS, the SS-DPLL achieves phase noise performance of −109 dBc/Hz at 1 MHz offset, while consuming a record-low power of 1.19 mW. [ABSTRACT FROM AUTHOR]