Search

Gallium Nitride (GaN) power devices can offer better switching performance and higher efficiency than Silicon Carbide (SiC) and Silicon (Si) devices in power electronics applications. GaN has extensively been incorporated in electric vehicle charging stations and power supplies, subjected to harsh environmental conditions. Many reliability studies evaluate GaN power devices through thermal stresses during current conduction or pulsing, with a few focusing on high blocking voltage and high humidity. This paper compares GaN-on-Si High-Electron-Mobility Transistors (HEMT) device characteristics under a High Humidity, High Temperature, Reverse Bias (H3TRB) Test. Twenty-one devices from three manufacturers were subjected to 85 °C and 85% relative humidity while blocking 80% of their voltage rating. Devices from two manufacturers utilize a cascade configuration with a silicon metal-oxide-semiconductor field-effect transistor (MOSFET), while the devices from the third manufacturer are lateral p-GaN HEMTs. Through characterization, three sample devices have exhibited degraded blocking voltage capability. The results of the H3TRB test and potential causes of the failure mode are discussed. [ABSTRACT FROM AUTHOR]

SiC SGTO thyristors are an advanced solution for increasing the power density of medium voltage power electronics. However, for these devices to replace Si thyristor technology in industrial applications their characteristics and failure modes must be understood. This letter presents the failure modes of two 15-kV SiC SGTO thyristors during repetitive overcurrent conditions. The devices were evaluated with 2-kA (3.85 kA/cm2) square pulses of 100 \boldsymbol \mus duration using a pulse forming network. Throughout testing, each devices’ static characteristics were analyzed for signs of degradation; upon degradation, testing was ceased and the physical failure mode was determined through imaging with a scanning electron microscope (SEM) in conjunction with a focused ion beam. The electrical results demonstrate the failure modes of both SiC SGTO thyristors during pulsed overcurrents electrically manifested themselves as a conductive path through the gate-anode junction and an increased device on-state voltage. SEM imaging revealed one SiC thyristor formed an approximately 10\-\mum wide cylindrical void, and the second SiC thyristor formed an approximately 200\-\mum long crack. However, the experimental results demonstrate these 15-kV SiC SGTO thyristors’ robust ability to repetitively switch at extreme high current density for tens of thousands of cycles. [ABSTRACT FROM AUTHOR]

SiC MOSFETs are a leading option for increasing the power density of power electronics; however, for these devices to supersede the Si insulated-gate bipolar transistor, their characteristics have to be further understood. Two SiC vertically oriented planar gate D-MOSFETs rated for 1200 V/150 A were repetitively subjected to pulsed overcurrent conditions to evaluate their failure mode due to this common source of electrical stress. This research supplements recent work that demonstrated the long term reliability of these same devices [1]. Using an RLC pulse-ring-down test bed, these devices hard-switched 600 A peak current pulses, corresponding to a current density of 1500 A/cm2. Throughout testing, static characteristics of the devices such as $B_{{\rm VDSS}}$ , $R_{{\rm DS}({\rm on})}$, and $V_{{\rm GS}({\rm th})}$ were measured with a high power device analyzer. The experimental results indicated that a conductive path was formed through the gate oxide; TCAD simulations revealed localized heating at the SiC/SiO2 interface as a result of the extreme high current density present in the device's JFET region. However, the high peak currents and repetition rates required to produce the conductive path through the gate oxide demonstrate the robustness of SiC MOSFETs under the pulsed overcurrent conditions common in power electronic applications. [ABSTRACT FROM PUBLISHER]

Presents a study which developed an operational technique, growth requirements and pn-pn-pn type structures to address the issues of high on-state voltage and other problems on breakover voltages in silicon carbide thyristors. Procedures for the fabrication of thyristors; Discussion; Results.

The high-voltage silicon carbide MOSFET is a state-of-the-art solution for increasing power density and efficiency in power electronics; nonetheless, a full-scope of failure modes during extreme operating condition has not been established. Past efforts evaluated short-circuit capability of 10-kV silicon carbide MOSFET, however, in this manuscript, the single-pulse avalanche mode operation of a research-grade 10-kV/10-A silicon carbide MOSFET is explored for the first time. A decoupled unclamped inductive circuit was selected for evaluation, and avalanche energy was increased until catastrophic failure occurred. The maximum tolerable avalanche energy was measured to be 2.84 J corresponding to an energy density of 8.8 J·cm −2 . This result was compared with 1.2-kV silicon carbide MOSFETs to evaluate device robustness. Post failure analysis included: estimation of junction temperature, scanning electron microscopy, and focused ion beam cut. Peak junction temperature of 1010 °C was estimated using a thermal RC model and measurement results suggested gate degradation as the primary mechanism responsible for device destruction. Microscopy of the device validated gate failure which occurred at, or beneath, the gate metallization. A narrow cavity with-in the failure region was discovered during failure analysis and is hypothesized to have protruded the epitaxial region of the semiconductor. [ABSTRACT FROM AUTHOR]