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Vertical diamond Schottky diodes with blocking voltages VBD > 2.4kV and ON-resistances RON < 400m Ω cm2 were fabricated on homoepitaxially grown diamond layers with different surface morphologies. The morphology (smooth as-grown, hillock-rich, polished) influences the Schottky barrier, the carrier transport properties, and ultimately the device performance. The smooth as-grown sample exhibited a low reverse current density JRev < 10−4 A/cm2 for reverse voltages up to 2.2 kV. The hillock-rich sample blocked similar voltages with a slight increase in the reverse current density (JRev < 10−3 A/cm2). The calculated 1-D breakdown field, however, was reduced by 30%, indicating a field enhancement induced by the inhomogeneous surface. The polished sample demonstrated a similar breakdown voltage and reverse current density as the smooth as-grown sample, suggesting that a polished surface can be suitable for device fabrication. However, statistical analysis of several diodes of each sample showed the importance of the substrate quality: a high density of defects both reduces the feasible device area and increases the reverse current density. In forward direction, the hillock-rich sample exhibited a secondary Schottky barrier, which could be fit with a modified thermionic emission (TEM) model employing the Lambert W-function. Both polished and smooth samples showed nearly ideal TEM with ideality factors 1.08 and 1.03, respectively. Compared with the literature, all three diodes exhibit an improved Baliga figure of merit for diamond Schottky diodes with VBD > 2 kV. [ABSTRACT FROM AUTHOR]

Tomorrow's power electronic systems require cost‐saving and more efficient power conversion solutions. The heterogeneous integration of GaN‐based high electron mobility transistors (HEMTs) together with silicon CMOS by micro‐Transfer‐Printing could be a key technology for this. It enables the integration of highly integrated mature CMOS logic functionality with fast GaN HEMT output drivers with very low on‐state and switching losses. The scalability by design measures of the printed HEMT is investigated in terms of drain‐to‐gate spacing and channel width defining breakdown voltage and area‐related parameters like on‐resistance. The design flexibility of the micro‐Transfer‐Printing by printing the HEMTs on top of the CMOS devices without restrictive design rule limits is investigated by CMOS DC parameter comparison and thermal TCAD Design Of Experiment (DOE) study. No electrical or thermal functional limitation of printing the HEMTs directly on top of the CMOS dielectric layer stack was found. This enables the usage of the isolation capabilities of the CMOS dielectric layer stack to enhance the HEMT breakdown voltage. [ABSTRACT FROM AUTHOR]