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The design of a 200-A, all-SiC power-module-based on bipolar junction transistor devices is described, and the impact of the module is assessed on the performance of a 50-kW dc-dc converter for electric vehicle applications, particularly the overall weight and efficiency. Using a hard-switching dual-interleaved topology, which has proven high efficiency and high-power density capability, the operation of a 50-kW, 75-kHz all-SiC converter is compared with that of an insulated-gate bipolar transistor-based silicon converter, switching at 25 kHz, each providing 600-V output. The results show that the total losses are reduced by almost 40%, whilst the overall weight is reduced by 27%, achieving a power density of 10.5 kW/kg. Experimental results of the SiC converter operating at 220-600 V, 52.8 kW are provided, showing an efficiency of 97%. [ABSTRACT FROM AUTHOR]

Fundamental frequency techniques are used to analyze the series-parallel resonant converter under heavy load conditions, both with a continuous, but distorted parallel capacitor voltage waveform, and with a discontinuous capacitor voltage waveform. The analysis is validated with results from an experimental prototype. The application of the technique to the parallel-loaded L-C resonant converter is also considered. [ABSTRACT FROM AUTHOR]

A split-core technique is proposed to mitigate the gap losses in high-frequency nanocrystalline cores, which enables significant size reductions in thermally limited designs. Finite element analysis is used to examine the gap loss dependence on core width D revealing a nonlinear relationship of the form loss ∝ $D^{\alpha }$. α is approximately constant for frequencies of 10–200 kHz over the range of core widths typically used in power electronics, but α increases with gap length. Splitting the core into a number of subcores can therefore provide significant reductions in gap loss, especially with larger gap lengths. The results from a 300-A (peak), 200-A (continuous) inductor show that with three subcores and a gap length of 4 mm, the gap losses are reduced by 50%, and the hot-spot temperature is reduced by 24.5 °C. Using the technique it is estimated that the original inductor weight could be reduced by 40% with four split cores, making a significant impact on converter power density. [ABSTRACT FROM AUTHOR]

Finite element analysis is used to examine the gap losses that occur in finely laminated nanocrystalline inductor cores under high-frequency operation. The losses are seen to be concentrated in the region of the air gap and the dependence of the losses on key design parameters and operating conditions is explored. The results show that gap losses can be significant in this type of core, creating hot spots around the gap, and the losses are not accurately predicted by established design equations for low-frequency laminated cores. A modified loss equation is proposed. Validation is provided by measurements on a 300-A, 60 kHz inductor. [ABSTRACT FROM AUTHOR]

Accurately predicting the temperature of semiconductor devices is very important in the initial design of the power electronics converter. RC thermal models derived from the well-known methods have some ability to predict the temperature. However, the accuracy is boundary condition specific; hence, these methods cannot be used in the reliability analysis. To make the thermal model more accurate and robust, the factors contributing to discrepancies need to be analyzed carefully. These are power-module-materials’ nonlinear properties, thermal grease layer, and the cooling system (i.e., liquid-cooled cold plate). In this article, the estimation of accurate RC parameters from the FEA thermal model is demonstrated in COMSOL. The electrical model having temperature-dependent power loss model is coupled to a refined thermal model and solved in a circuit simulator, PLECS. The proposed method is applied in two applications: assessing thermal interaction between IGBTs and antiparallel diodes in a half-bridge power module and assessing thermal interaction among the discrete switches in an interleaved bidirectional dc–dc converter. Results show that the impact of material nonlinearity, thermal grease layer, and cooling boundary conditions are significant for accurate prediction of IGBT and diode temperatures. The proposed model is consistent with FEA results and differs by 2%–6.5% compared with the experimental results. [ABSTRACT FROM AUTHOR]

All-GaN-integrated cascode heterojunction field effect transistors were designed and fabricated for power switching applications. A threshold voltage of +2 V was achieved using a fluorine treatment and a metal–insulator–semiconductor gate structure on the enhancement mode part. The cascode device exhibited an output current of 300 mA/mm by matching the current drivability of both enhancement and depletion mode parts. The optimization was achieved by shifting the threshold voltage of the depletion mode section to a more negative value with the addition of a dielectric layer under the gate. The switching performance of the cascode was compared to the equivalent GaN enhancement-mode-only device by measuring the hard switching speed at 200 V under an inductive load in a double pulse tester. For the first time, we demonstrate the switching speed advantage of the cascode over equivalent GaN enhancement-mode-only devices, due to the reduced Miller-effect and the unique switching mechanisms. These observations suggest that practical power switches at high power and high switching frequency will benefit as part of an integrated cascode configuration. [ABSTRACT FROM AUTHOR]