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In this study, to solve total harmonic distortion (THD) and voltage stress on switches, challenges have been made by presenting a new multi‐level inverter (MLI). The proposed topology can operate with both symmetric and asymmetric sources. The proposed topology in symmetric and asymmetric mode with 18 switches can produce 17 and 49 voltage levels, respectively, with THD values of 4.14% and 1.45%, which passes the IEEE harmonic standard. The main advantage of the proposed topology is reducing the number of circuit devices, which reduces the price, volume, and complexity of the circuit by reducing the number of circuit devices. The proposed topology reduces the THD, the number of power electronics components, and voltage stress by increasing the output levels. The proposed topology is compared with other topologies and the advantage of the proposed topology is shown in terms of the number of switches and drivers. In addition, the proposed topology is compared in terms of the cost function. The power losses based on the thermal model of the proposed topology have been analysed and simulated. Simulation and experimental results are presented for different scenarios such as load type, load changes, and modulation index changes to validate the proposed topology. [ABSTRACT FROM AUTHOR]

Today, multilevel inverters are widely utilized in various applications. Reducing the number of components in the design of these converters is one of the crucial goals so that they have less volume and cost. This paper presents a single‐source structure for a multilevel switched‐capacitor inverter with voltage boost capability. The proposed structure can generate 25 sinusoidal‐like step voltage levels with a six times amplitude increase compared to the input. This converter uses only one direct current (DC) power source, 14 switches, and four capacitors. The nearest level control switching method has been used to control the converter, create voltage levels, and select the switching modes. A comprehensive comparison has been made with other recently presented structures to demonstrate the efficiency of the proposed structure. The advantages of the proposed structure include using only one DC voltage source, the ability to increase the output voltage six times compared to the input, the use of fewer power electronics components compared to the number of voltage levels, proper efficiency, self‐balancing of capacitors, and as a result, the lower cost. The performance accuracy of the proposed converter has been simulated in the MATLAB Simulink environment and then evaluated by a laboratory prototype. [ABSTRACT FROM AUTHOR]

Utilization of small-scale wind energy conversion systems (WECS) has been grown in recent years. Permanent magnet synchronous generator due to lack of slip rings is a suitable alternative for induction generators to be used in these systems. However, these generators use full power converters which means higher power losses. In this paper, an ultra-efficient three-level converter, called T-type converter, is used in a back-to-back configuration as power electronic interface for PMSG-based small-scale WECS. Then, simulations are carried out to evaluate the efficiency of the system and compare it to conventional two- and three-level back-to-back configurations. Meanwhile, thermal analysis is carried out to investigate the thermal loading of different switching components of the converter. Data given by this analysis can be further used to evaluate system reliability. Therefore, system reliability is calculated and compared to conventional two- and three-level converter systems. [ABSTRACT FROM AUTHOR]

Multilevel inverters are a new generation of DC–AC converters at medium and high voltage and power levels. In this paper, a new single-phase cascaded multilevel inverter is presented. For this purpose, a new basic cell is presented at first. Then, the new multilevel inverter structure is yielded by series connection of these cells. The proposed new cell is only capable of generating positive voltage levels, and therefore, to produce zero and negative voltage levels, the proposed structure is constructed based on H-bridge module. In order to reduce the maximum blocking voltage especially on H-bridge switches, the cascaded connection of the proposed converter is investigated. A comprehensive comparison is carried out between the proposed multilevel inverter with the classical and recently introduced structures in terms of the number of switching devices, the number of drivers, the total blocking voltage of the switches as well as the loss and efficiency. The accuracy of the proposed inverter's performance is simulated in MATLAB/Simulink in symmetric and asymmetric topologies for a 17-level and 23-level output voltage respectively, and then evaluated by the laboratory prototype. [ABSTRACT FROM AUTHOR]

Summary Multilevel inverters are known as essential converters in renewable sources. First, in this paper, a new submodule is presented, and based on it, a new sub‐multilevel inverter is presented. The proposed sub‐multilevel inverter consists of several unidirectional and bidirectional switches and DC voltage sources. Then, the generalized topology, developed in two modular and cascaded modes, is presented to increase production levels. The proposed submodules are connected in series in the modular topology, increasing production levels. The proposed topology to produce the maximum output levels has the minimum number of IGBTs, drivers, DC voltage sources, etc. Mathematical analyses for conduction and switching losses are provided, and mathematical analyses for the number of devices and voltage across the switches are also presented. In addition to the mathematical analysis of losses, the simulation results are also presented. A general comparison of proposed topology components is presented to demonstrate their advantages. This comparison shows that the proposed topology has the minimum number of power electronic devices. In this paper, nearest level modulation is used to control the proposed topology. The simulation and experimental results of the proposed sub‐multilevel verify the performance of the proposed topology. [ABSTRACT FROM AUTHOR]