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This brief discusses the impact of twin- and triple-well structures on power supply noise, and a substrate model for simulating the power supply noise. We observed Vss noise reduction by the resistive network of the p-substrate and Vdd noise reduction by the junction capacitance of a triple-well structure on a 90-nm test chip. Measurement results also showed that the total noise reduction of a triple-well structure is superior to that of a twin-well structure. The measurement results correlate well with the results obtained from the power supply noise simulation using a hierarchical resistive mesh model. Our simulation-based verification indicates that in common CMOS design, a triple-well structure can reduce the power supply drop by 10%–40% or the decoupling capacitance area by 5%–10%. We also verified that supply drop sensitivity to variation of the well junction capacitance is sufficiently small and that supply noise reduction using a triple-well structure is robust to process variation. [ABSTRACT FROM PUBLISHER]

In this paper, the soft error rate (SER) induced by neutrons in 65-nm 10T static random access memory (SRAM) is measured over a wide range of supply voltages from 1.0 to 0.3 V. The results show that the neutron-induced SER at 0.3 V is around eight times that at 1.0 V. The dependence of multiple cell upsets (MCUs) on the supply voltage and on the distance between well ties is also investigated. The dependence of the MCU rate on the supply voltage between 1.0 and 0.5 V is small and increases as the voltage is reduced below 0.5 V. This is because the effect of another mechanism, such as charge-sharing, becomes larger in the subthreshold region, rather than the parasitic bipolar effect, which is considered the dominant mechanism causing MCUs in SRAM at the nominal supply voltage in our design. [ABSTRACT FROM AUTHOR]

Abstract-This paper proposes an all-digital measurement circuit called a "gated oscillator" to capture the waveforms of dynamic power supply noise. An improved gated oscillator with a power-gating structure is also proposed. The gated oscillator is constructed using standard cells, and thus is easily embedded in SoCs. Its performance was evaluated using test chips fabricated in a 90 nm process. The gated oscillator achieved 5.3-5.9 Gsample/s with an area of 10.08 x 6.72 μm[sup2], and the improved power gating structure achieved 6.6-8.3 Gsample/s in a 90 nm process. The characteristics of the gated oscillator and related design issues are also discussed. These characteristics were verified on silicon. We evaluated the effect of the decoupling capacitance based on measurement results obtained using the gated oscillator, and demonstrated that it could be used to verify power integrity. [ABSTRACT FROM AUTHOR]

This paper discusses a low-power-consumption architecture for the processor based on object code compression, especially the application of the idea to embedded processors. In the proposed method, duplicated instructions are unified to compress the program. An instruction decompression circuit is added, which reorganizes the object code from the pseudocode generated by the compression. The instruction decompression circuit and the processor are integrated into a single chip, which helps to reduce the bandwidth needed in the interface to the external memory. Then, the power consumption is reduced greatly. As a result of experiments, when the proposed method is applied to the ARM610 32-bit RISC processor, the code is compressed by 62.5%. The power consumption in the instruction memory is reduced by 42.3%. The area of the instruction decompression circuit that is additionally implemented is 0.983 mm2. © 1998 Scripta Technica, Electron Comm Jpn Pt 3, 81(10): 83–90, 1998 [ABSTRACT FROM AUTHOR]