Search

Three large-area 10-kV 4H-SiC DMOSFET designs are compared with respect to their design, die area, breakdown yield, and ON-state yield. The largest of these DMOSFETs had 0.62 cm² of active area on a 1-cm² die, with a 10-kV device producing 40 A at a gate field of 3 MV/cm. Two designs used linear interdigitated fingers, whereas the third design used a square cell layout. The linear interdigitated finger design proved to be more robust, with higher yields than the square cell geometry. It was determined that the square cell design was yield limited due to the impact of wafer bow and total thickness variations on photolithographic accuracy, making the square cell geometry less attractive for large-area 4H-SiC DMOSFETs. [ABSTRACT FROM AUTHOR]

This paper presents the development and demonstration of large-area 10-kV 4H-SiC DMOSFETs that maintain a classically stable low-leakage normally off subthreshold characteristic when operated at ≤ 200 °C. This is achieved by an additional growth (epitaxial regrowth) of a thin epitaxial layer on top of already implanted p-well regions in conjunction with a N2 O-based gate oxidation process. Additionally, the design space of the DMOSFET structure was explored using analytical and numerical modeling together with experimental verification. The resulting 0.15-cm² active 0.43-cm² die DMOSFET with 10-kV breakdown provides IDS = 8 A at a gate field of 3 MV/cm, along with a subthreshold current at VGS = 0 V that decreases from 1 μA (6.7 μA/cm²) at 25 °C to 0.4 μA (2.7 μA/cm²) at 200 °C. [ABSTRACT FROM AUTHOR]