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Unipolar sinusoidal pulsewidth modulation (SPWM) full-bridge inverter brings high-frequency common-mode voltage, which restricts its application in transformerless photovoltaic grid-connected inverters. In order to solve this problem, an optimized full-bridge structure with two additional switches and a capacitor divider is proposed in this paper, which guarantees that a freewheeling path is clamped to half input voltage in the freewheeling period. Sequentially, the high-frequency common-mode voltage has been avoided in the unipolar SPWM full-bridge inverter, and the output current flows through only three switches in the power processing period. In addition, a clamping branch makes the voltage stress of the added switches be equal to half input voltage. The operation and clamping modes are analyzed, and the total losses of power device of several existing topologies and proposed topology are fairly calculated. Finally, the common-mode performance of these topologies is compared by a universal prototype inverter rated at 1 kW. [ABSTRACT FROM AUTHOR]

This letter proposes a fast current control scheme for ac drives by minimizing the latency from current sampling to the updation of a pulsewidth-modulation (PWM) command. By reconstructing the architecture of a linear controller, the minimal necessary steps to obtain the output voltage are deduced as the primary calculation, and the other computation work of the current loop is done in the postcalculation after updating the PWM command. With the proposed method, the computational delay is reduced with negligible loss in the available modulation index, and a higher stability margin or system bandwidth is realized. Also, the developed controller structure exhibits inherited antiwindup characteristics. The technique has been validated by experimental investigations on a permanent magnet synchronous motor. [ABSTRACT FROM AUTHOR]

This article proposes an improved space vector modulation (SVM) for the current-source rectifier (CSR). Due to the overlap time during commutations of power switches, the pulsewidth-modulation (PWM) currents of CSR may suffer from a number of low-order (mainly fifth and seventh) harmonics, which seriously degrade the harmonic performance of currents and voltages on the grid side. Especially, the overlap-time effect becomes an important issue when the increased switching frequency is applied to CSR. To mitigate these low-order harmonics of the PWM converter currents resulted from the overlap-time effect, the relationship between the overlap time and the low-order harmonics in PWM currents and grid currents are analyzed at first. Then, the design process of the LC filter and the proposed SVM with optimal overlap-time distribution is presented in details. Finally, experimental results are conducted on a low power laboratory prototype to verify the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]