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The carrier-based pulse width modulation (CBPWM) with zero-sequence component injection is equivalent to the space-vector PWM (SVPWM), and hence it can be taken as a simplified alternative to the SVPWM. However, it is quite complex to calculate the zero-sequence component in CBPWM for three-level (3L) converters such as the T-type converter, making the 3L SVPWM still have a large computation burden. In this letter, unified expressions for the zero-sequence component are analytically derived, and the modulation waves of 3L SVPWM can be directly calculated by only 7 simple equations with 3 steps. The computation burden for implementing 3L SVPWM is therefore significantly reduced without sector determination, calculation and assignment of dwell times. [ABSTRACT FROM AUTHOR]

No dead-time is contained in the existing dead-time elimination pulsewidth modulation (PWM) for three-phase three-level T-type converters, where complementary drive pulses are allocated alternatively according to polarities of output currents. Consequently, the dead-time effect can be inherently avoided. However, the dependency on current polarities seriously limits its widespread application. Wrong current polarities, e.g., in a dynamic process, will lead to the output-voltage disappearance, thus aggravating the possible “algebraic loop” issue and impairing the stability of the system. In this article, in order to reduce the dependency on current polarities while retaining the characteristic of dead-time-effect elimination, a double-modulation-wave PWM is proposed by modifying the dead-time elimination PWM. Two modulation waves with a magnitude difference are adopted for generating underlap periods between complementary drive pulses, which can avoid the shoot-through failure and no dead-time effect will be generated. And to further simplify the implementation process, the two modulation waves are decomposed by introducing a magnitude-adjustment factor related to the current polarity. Whereas it is also due to the employment of two modulation waves, extra issues of overmodulation, single drive pulses, and a shorter underlap period may occur, which are analyzed in detail and the negative effect can be avoided. Finally, the proposed PWM is experimentally verified, showing the effectiveness on harmonic suppression and the reduced dependency on current polarities. [ABSTRACT FROM AUTHOR]

Given the high complexity of the conventional three-level space-vector pulsewidth modulation (3L SVPWM), simplified SVPWM algorithms are usually adopted instead. However, existing simplifications for 3L SVPWM still have a large computation burden, which limits its applications, e.g., in high-switching-frequency silicon-carbide converters with a short computation period. In this letter, based on a typical simplified algorithm known as the center-aligned 3L SVPWM, a simplified analytical algorithm in abc coordinate is proposed. The reference-voltage-vector adjustment and the calculation of modulation waves are unified based on the center-aligned SVPWM. The modulation waves can be analytically derived by only eight simple equations, without sector determination, calculation, and assignment of dwell times. Consequently, the complexity of implementing the 3L SVPWM is significantly reduced. [ABSTRACT FROM AUTHOR]

The dead-time elimination pulsewidth modulation (PWM) enables the drive pulses of the upper and the lower switching devices to alternate according to the current polarity, thus abandoning the dead time and essentially avoiding the dead-time effect in power converters. However, the current zero crossing will be distorted by the current jump generated by the drive-pulse alternation, and the current zero-crossing distortion will be further intensified if errors exist in the detected current polarity. Thanks to the noise-attenuation and frequency-adaptability characteristics of the double second-order generalized integrator frequency-locked loop (DSOGI-FLL), it can obtain accurate current polarities even in harmonic and unbalanced conditions. A DSOGI-FLL-based dead-time elimination PWM is, therefore, proposed in this paper, and several improvements are made to minimize the current zero-crossing distortion. An underlap period is added when alternating the upper and lower drive pulses to smooth the current jump at zero crossing, and a delay compensation term is inserted in the DSOGI-FLL to compensate both the current measurement delay and the control delay. The effectiveness of the proposed DSOGI-FLL-based dead-time elimination PWM has been validated by experiments, respectively, in the unbalanced-current, power-change, and frequency-variation conditions with an RL load, as well as in a grid-connected converter. [ABSTRACT FROM AUTHOR]