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A Neutral Point Clamped (NPC) type three-level inverter has the advantages of a low switch voltage and a high-quality output waveform. However, there are inherent problems, such as neutral point potential asymmetry and common mode interferences, which easily affect the symmetry of the three-phase output voltage and the safe operation of the inverter. Firstly, according to the different modulation degrees, the fluctuation of midpoint potential can be suppressed by adding an action time correction factor to the traditional space vector pulse-width (SVPWM) modulation strategy and virtual space vector pulse-width (VSVPWM) modulation strategy, respectively. Secondly, considering the suppression of common mode voltage, a new virtual space vector pulse-width (NVSVPWM) modulation strategy is proposed, which uses a set of new vector synthesis methods. Finally, the simulation and experiment prove that the NVSVPWM strategy with an action time correction factor can suppress the fluctuation of the neutral point potential and common mode voltage at the same time, and the effect is significant. [ABSTRACT FROM AUTHOR]

In a three-phase three-level grid-connected inverter, the ac output current ripple actually fluctuates four times per switching period with each fluctuation generating some core loss. However, only the two larger fluctuations are considered in most loss estimation methods, resulting in a smaller core loss evaluation. In this letter, an alternative method has, hence, been proposed, beginning with the deduction of fundamental and ripple equivalent circuits from the inverter. These circuits permit current ripple to be calculated, from which its four fluctuations are all considered for forming the dual current-ripple envelopes (DCREs). These DCREs, together with the fundamental current and a selected core loss model, can then be solved to give the estimated fundamental and ripple core loss values. The nonlinear characteristic of the filter inductor has also been considered in the calculation of the DCREs and the core loss. The estimated values have eventually been verified through testing with a 10-kW three-phase T-type three-level grid-connected inverter. [ABSTRACT FROM AUTHOR]

The dead-time elimination pulsewidth modulation (PWM) enables the drive pulses of the upper and the lower switching devices to alternate according to the current polarity, thus abandoning the dead time and essentially avoiding the dead-time effect in power converters. However, the current zero crossing will be distorted by the current jump generated by the drive-pulse alternation, and the current zero-crossing distortion will be further intensified if errors exist in the detected current polarity. Thanks to the noise-attenuation and frequency-adaptability characteristics of the double second-order generalized integrator frequency-locked loop (DSOGI-FLL), it can obtain accurate current polarities even in harmonic and unbalanced conditions. A DSOGI-FLL-based dead-time elimination PWM is, therefore, proposed in this paper, and several improvements are made to minimize the current zero-crossing distortion. An underlap period is added when alternating the upper and lower drive pulses to smooth the current jump at zero crossing, and a delay compensation term is inserted in the DSOGI-FLL to compensate both the current measurement delay and the control delay. The effectiveness of the proposed DSOGI-FLL-based dead-time elimination PWM has been validated by experiments, respectively, in the unbalanced-current, power-change, and frequency-variation conditions with an RL load, as well as in a grid-connected converter. [ABSTRACT FROM AUTHOR]