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Identification of the defective patterns of the wafer maps can provide insights for the quality control in the semiconductor wafer fabrication systems (SWFSs). In real SWFSs, the collected wafer maps are usually imbalanced from the defective types, which will result in misidentification. In this paper, a novel deep learning model called adaptive balancing generative adversarial network (AdaBalGAN) is proposed for the defective pattern recognition (DPR) of wafer maps with imbalanced data. In addition, a categorical generative adversarial network is improved to generate simulated wafer maps in high fidelity and classify the patterns with high accuracy for all defective categories. Taking consideration of the various learning abilities of the DPR model for different patterns into account, an adaptive generative controller is designed to balance the number of samples of each defective type according to the classification accuracy. The experiment results indicated that the proposed AdaBalGAN model outperforms conventional models with higher accuracy and stability for the DPR of wafer maps. Further results of comparative experiments revealed that the proposed adaptive generative mechanism can enhance and balance the recognition accuracy for all categories in the DPR of wafer maps. [ABSTRACT FROM AUTHOR]

In modern semiconductor manufacturing, one type of measured particle count data contains excess zeros, and the ratio of zeros in the measurements is usually larger than 50%. This type of particle count sample data cannot be well modeled by popular defect models such as Poisson, zero-inflated Poisson, generalized zero-inflated Poisson, and Neyman and Gamma-Poisson models. In this paper, a threshold-Poisson model was proposed to describe the particles with excess zero counts, and the method for parameter estimation was developed. Via comparison with those popular models by using 15 measured samples, it showed that the measurements are better modeled by the threshold-Poisson model. A control chart called threshold-c control chart was proposed and the control limits were derived. A reasonable minimum sample size for constructing control chart was also discussed based on simulations. [ABSTRACT FROM AUTHOR]

In this paper, some practical considerations for effective and efficient wafer-level reliability control (WLRC) are presented. We propose a better solution to replace the previous method by adding a protection diode to avoid process induced charging damage on test structure devices. This work also provides in-depth discussions on WLR Via electromigration (EM), which correlated well with traditional time-consuming package-level tests. In addition, due to the time constraint at WLRC, some real cases are discussed regarding the suitable sampling plan and test structures. These studies are to improve WLRC effectiveness and efficiency, to diagnose reliability concerns, to expedite WLRC failure analyses when out-of-control, and, thus, to facilitate WLRC lot dispositions. [Copyright &y& Elsevier]