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In this article, a moving accumulative sign filter (MASF) voter model and a low-power serial voting circuit are proposed for high-speed clock data recovery (CDR). Different from the previously reported parallel voter and moving average majority voter (MV), the proposed design is based on the MASF algorithm and adopts a two-stage voting structure. Only D-flip-flop (DFF) and basic logic gates are used to realize the serial voting function of the four continuous lead/lag/hold decision signals. The proposed MV realizes the signal processing of the four-phase error information without using traditional gain and quantization operations. In addition, by eliminating the redundant output state, the input noise of the digital filter of CDR can be reduced, which could also reduce the power consumption of the subsequent circuits due to less logical flips. As a result, the proposed serial MV can operate at a half baud rate in a high-speed CDR and it can reduce the chip area by removing the demultiplexer unit and the moving average filter. The proposed MV circuit is implemented for a high-speed CDR using a 40-nm CMOS process, which shows a 12-GHz maximum operating speed. The measured power consumption of the whole voter at 10 GHz is only 0.55 mW and the core chip area is $8.6\,\times \,25.4\,\,\mu \text{m}^{2}$. [ABSTRACT FROM AUTHOR]

To improve the SpO2 sensing system performance for hypoperfusion (low perfusion index) applications, this paper proposes a low-noise light-to-frequency converter scheme from two aspects. First, a low-noise photocurrent buffer is proposed by reducing the amplifier noise floor with a transconductance-boost (gm-boost) circuit structure. Second, a digital processing unit of pulse-frequency-duty-cycle modulation is proposed to minimize the quantization noise in the following timer by limiting the maximum output frequency. The proposed light-to-frequency sensor chip is designed and fabricated with a 0.35- μm CMOS process. The overall chip area is 1 × 0.9 mm2 and the typical total current consumption is about 1.8 mA from a 3.3-V power supply at room temperature. The measurement results prove the proposed functionality of output pulse duty cycle modulation, while the SNR of a typical 10-kHz output frequency is 59 dB with about 9-dB improvement when compared with the previous design. Among them, 2–3 dB SNR improvement stems from the gm-boosting and the rest comes from the layout design. In-system experimental results show that the minimum measurable PI using the proposed blood SpO2 sensor could be as low as 0.06% with 2-percentage-point error of SpO2. The proposed chip is suitable for portable low-power high-performance blood oximeter devices especially for hypoperfusion applications. [ABSTRACT FROM AUTHOR]

Sensor interfaces demand ever-increasing energy efficiency from analog-to-digital converters (ADCs). For sensors requiring a wide dynamic range (DR) (>12 bit), the incremental ADC (IADC) is becoming a popular choice. In this article, the design of an energy-efficient IADC with a 16-bit signal-to-noise and distortion ratio (SNDR) and 17-bit DR is described. The IADC implements a novel capacitor scaling technique, which reduces power consumption in the critical first operational transconductance amplifier (OTA) by up to 37%. The new technique can be combined with the extended counting (EC) scheme utilizing an in-loop 4-bit asynchronous successive approximation register (SAR) (ASAR) ADC. Using a three-phase operation, this IADC architecture further reduces the power while enabling wider signal bandwidth with a much lower oversampling ratio (OSR). Silicon measurements in a 0.18- $\mu $ m CMOS process show the IADC achieved a DR of 102.2 dB, within a bandwidth of 2.04 kHz, with power consumption of about $25~\mu $ W, leading to a state-of-the-art Schreier figure-of-merit (FoM) of 181.1 dB. [ABSTRACT FROM AUTHOR]

In this paper, we propose a lossy image compression algorithm called microshift. We employ an algorithm-hardware co-design methodology, yielding a hardware-friendly compression approach with low power consumption. In our method, the image is first micro-shifted, and then the sub-quantized values are further compressed. Two methods, FAST and MRF models, are proposed to recover the bitdepth by exploiting the spatial correlation of natural images. Both methods can decompress images progressively. On an average, our compression algorithm can compress images to 1.25-bits per pixel with a resulting quality that outperforms the state-of-the-art on-chip compression algorithms in both peak signal-to-noise ratio and structual similarity. Then, we propose a hardware architecture and implement the algorithm on an FPGA. The results on the ASIC design further validate the low-hardware complexity and high-power efficiency, showing that our method is promising, particularly for low-power wireless vision sensor networks. [ABSTRACT FROM AUTHOR]

This paper presents a low-power column-parallel inverter-based cyclic analog-to-digital converter (ADC) for CMOS image sensor readout circuit. By partially floating the capacitors inside the multiply digital-analog-converter during the least significant bit (LSB) quantization, the amplifier load capacitance could be significantly scaled down, which allows much higher settling speed and shorter cycle period. Since the signal-to-noise ratio for LSB cycle is relaxed due to the residual amplification, the proposed capacitance scaling only contributes ignorable input-referred quantization noise. Using the proposed techniques, a cyclic ADC can operate under 50% power consumption without suffering conversion rate, noise performance, and linearity. A 12-b quantization resolution test chip is fabricated using the TSMC 0.18- \mu \textm technology with 110 column-parallel ADC channels and 10.08- \mu \textm \times 750 - \mu \textm column pitch. The 3.5/−2 LSBs integral nonlinearity and 10.1-b effective-number-of-bit are measured under 2- \mu \texts sampling rate with 120- \mu \textW power consumption per channel. [ABSTRACT FROM AUTHOR]