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The execution of quantum algorithms requires two key considerations. On the one hand, it should meet the connectivity constraint requirements of quantum circuit mapping for quantum architectures, and on the other hand, it needs to consider reducing the probability of errors in the execution of quantum circuits as much as possible. This paper proposes a novel optimization technique based on template matching that to satisfy both requirements. The template matching optimization method can significantly reduce the number of gates in a quantum circuit and further enhance its practicality. It stands as advanced optimization technology available today. Our method optimizes quantum logic circuits mapped onto quantum architecture by initially selecting their linear substructure. We then zone the circuit according to the gate dependency graph and optimize each block through template matching. Finally, we reorganize the circuit to obtain the optimized version as the final result. Our proposed method is amenable to various quantum architectures. To evaluate its efficacy, we conduct a comparative analysis with the t|ket〉 and Qiskit compiler using a set of benchmark test circuits. Specifically, compare to the t|ket〉 compiler method, the highest average optimization rate of our method can reach 25.75%. Compare with the Qiskit compiler method, the highest average optimization rate can reach 32.72%. Overall, our approach has significant optimization advantages. [ABSTRACT FROM AUTHOR]

Crosstalk is the primary source of noise in quantum computing equipment. The parallel execution of multiple instructions in quantum computation causes crosstalk, which causes coupling between signal lines and mutual inductance and capacitance between signal lines, destroying the quantum state and causing the program to fail to execute correctly. Overcoming crosstalk is a critical prerequisite for quantum error correction and large-scale fault-tolerant quantum computing. This paper provides an approach for suppressing crosstalk in quantum computers based on multiple instruction exchange rules and duration. Firstly, for the majority of the quantum gates that can be executed on quantum computing devices, a multiple instruction exchange rule is proposed. The multiple instruction exchange rule reorders quantum gates in quantum circuits and separates double quantum gates with high crosstalk on quantum circuits. Then, time stakes are inserted based on the duration of different quantum gates, and quantum gates with high crosstalk are carefully separated in the process of quantum circuit execution by quantum computing equipment to reduce the influence of crosstalk on circuit fidelity. Several benchmark experiments verify the proposed method's effectiveness. In comparison to previous techniques, the proposed method improves fidelity by 15.97% on average. [ABSTRACT FROM AUTHOR]

The size of quantum circuits is growing as quantum computing develops, yet the devices available today cannot handle the large-scale quantum computing problems. Distributed quantum computing is an effective way to solve this problem. How to efficiently reduce the transmission cost of distributed quantum circuits is crucial because it serves as a fundamental standard of the effectiveness of distributed quantum computing. To this end, this research suggests a distributed storage pattern and a merged transfer model. Based on this distributed storage pattern, the quantum circuit matches the appropriate architecture for distribution, and the circuit is initially partitioned. To determine the most effective partitioning scheme for the circuits, a genetic algorithm is employed to reorder qubits and partition distributed circuits. Based on the merged transfer model, the exchange rules of quantum gates are used to combine a number of discontinuous gates into a single transmission through which these gates can be executed. The merged transfer model completes execution with fewer redundant transmissions, so as to achieve a lower transmission cost overall. The method proposed in this paper takes up fewer quantum resources and has a lower transmission cost than previous research results, with an average transmission cost optimization of 51.3%. [ABSTRACT FROM AUTHOR]

In order to implement a quantum circuit on an NISQ device, it must be transformed into a functionally equivalent circuit that satisfies the device's connectivity constraints. However, NISQ devices are inherently noisy, and minimizing the number of SWAP gates added to the circuit is crucial for reducing computation errors. To achieve this, we propose a subgraph isomorphism algorithm based on the timing weight priority of quantum gates, which provides a better initial mapping for a specific two-dimensional quantum architecture. Additionally, we introduce a heuristic swap sequence selection optimization algorithm that uses a distance optimization measurement function to select the ideal sequence and reduce the number of SWAP gates, thereby optimizing the circuit transformation. Our experiments demonstrate that our proposed algorithm is effective for most benchmark quantum circuits, with a maximum optimization rate of up to 43.51% and an average optimization rate of 13.51%, outperforming existing related methods. [ABSTRACT FROM AUTHOR]