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The total ionizing dose response of hybrid FinFET with a modified gate stack (GS) is investigated and examined for the various ultra-thin body (UTB) layers and combination of gate oxide stacks. Incorporation of UTB layer to the conventional FinFET enhances the mechanical strength of the device. While being irradiated, conventional FinFET with UTB layer reduces the accumulation of trap charges to a certain level. Further, reduction of these charges can be achieved by using a high-k dielectric with UTB layer. This reduction in interface trap charges enhance the OFF-state performance while maintaines the positive threshold voltage of the device. The combination of UTB and GS in SOI-FinFET renders it more reliable and tolerant to ionizing dose. • Total ionizing dose response of hybrid FinFET with a modified gate stack (GS) is investigated. • Incorporation of UTB layer to the conventional FinFET enhances the mechanical strength of the device. • Under radiation FinFET with UTB layer reduces the accumulation of trap charges. • Reduction in interface trap charges enhances the OFF state performance. • The combination of UTB and GS in SOI-FinFET renders it more reliable and tolerant to ionizing dose. [ABSTRACT FROM AUTHOR]

The effect total ionizing dose on a linear gate workfunction modulated SOI P-FinFET is analyzed and compared with the bulk P-FinFET. This technique improves the device electrostatic integrity for pre and post radiation condition. A decade improvement in I OFF is obtained for both the bulk and proposed devices. Moreover, both the SOI devices offer 35% and 29% less subthreshold swing for pre-rad condition. After irradiation trap charges are accumulated in oxide and semiconductor/insulator interfaces, which makes threshold more negative. The linear gate workfunction modulation gives more V th for both devices. At high radiation of 2000 krad dose proposed SOI device shows 39% more threshold voltage as compared to LGWM bulk P-FinFET. The maximum V th shift is observed in single workfunction bulk P-FinFET. Based on the simulation results, the proposed SOI P-FinFET is proved to be better TID tolerant and reliable. [ABSTRACT FROM AUTHOR]