Search

This article presents a full-duplex (FD) rake receiver (RX) that uses the orthogonality properties of pseudo-noise (PN) codes to reject transmitter (TX) self-interference (SI) in the RF domain, allowing simultaneous transmit and receive (STAR) operation in the same frequency channel. The rake RX also exploits multipath propagation in wireless channels and PN code orthogonality to gather signals across multipath components to increase the signal-to-noise ratio (SNR) while avoiding the fading effects of multipath channels. The rake RX shares a low-noise amplifier (LNA) between the three rake fingers and a high-linearity baseband (BB) section with the second-order filtering to improve the rejection with low power consumption. Measurements indicate that TX SI rejection is 41.2 dB in the RF domain with 9-dB SNR improvement in a multipath channel. The rake RX is implemented in a 45-nm RFSOI CMOS process and occupies an active area of 1.6 mm2 while consuming 45.8 mW per finger, including clock power consumption. [ABSTRACT FROM AUTHOR]

RF photonic components suffer from poor spurious-free dynamic range (SFDR) due to the high noise and distortion generated by a silicon photonic (SiP) Mach–Zehnder modulator (MZM). This work demonstrates a distributed silicon–germanium (SiGe) heterojunction bipolar transistor (HBT)-based low-noise amplifier (LNA) co-designed for linearization with a SiP MZM for a broadband radio-over-fiber (RoF) link. The SiGe LNA incorporates a distributed, tunable predistortion scheme that is inherently wideband and improves the third-order intercept point over an 18-GHz range. The assembled SiGe LNA and SiP MZM prototype demonstrates an SFDR as high as 120 dB ⋅ Hz2/3 at 9 GHz, a 14-dB improvement over previous SiP RF components or RoF links. [ABSTRACT FROM AUTHOR]

A code-domain transceiver front end that incorporates a transmit modulator and a receive (RX) RF signal correlator is presented. An integrate-and-dump $N$ -path filter improves rejection by 8 dB. We propose an RF chopper switch with 12.1-/23.1-dBm P1dB/IIP3 for both RF correlation and filtering that rejects TX self-interference by 49.5 dB. Walsh and Barker codes are generated with fine and coarse tuning for synchronization. The RX power consumption is 18 mW, including dynamic power (1-V supply) and four analog amplifiers (1.5 V) at the operating frequency of 1 GHz and the code rate of 200 megachip-per-second (Mc/s). The TX modulator operates to RF power levels up to 34.3 dBm and consumes less than 40 mW for 300 Mc/s. Over the air testing demonstrates synchronization with Barker codes. [ABSTRACT FROM AUTHOR]

High peak and average efficiency is an important feature of power amplifiers (PAs) for 5G millimeter-wave communication. This article reviews the challenges of conventional outphasing approaches in CMOS technologies and demonstrates a low-loss outphasing combiner for low loadline impedance. Undesirable characteristics of CMOS devices for outphasing are compensated with neutralization, unilaterization, and stabilization networks for the outphasing PA (OPA). The OPA is realized in 45-nm CMOS silicon on insulator (SOI) and demonstrates 40% 6-dB backoff drain efficiency (DE) while providing 17-dBm peak output power with a peak 50.5% DE. For 64-QAM, a 31.3% average DE and 10.1-dBm average output power are measured. The OPA demonstrates less than 1.5% error vector magnitude (EVM) with 64-QAM waveform using a phase-based lookup table (LUT). With 16-QAM, the bit rate reaches 20 Gb/s with 12% EVM. To the best of our knowledge, this is the highest bit rate for a high-efficiency PA. The adjacent channel leakage ratio (ACLR) is under −25 dBc. [ABSTRACT FROM AUTHOR]

Due to the heavy reliance of millimeter-wave (mmWave) wireless systems on directional links, beamforming (BF) with high-dimensional arrays is essential for cellular systems in these frequencies. Thus, performing the array processing in a power-efficient manner is a fundamental challenge. Analog and hybrid BF require few analog-to-digital and digital-to-analog converters (ADCs and DACs), but can only communicate in a small number of directions at a time, limiting directional search, spatial multiplexing, and control signaling. Digital BF enables flexible spatial processing but must be operated at a low quantization resolution to stay within reasonable power levels. This decrease in quantizer resolution distorts the received as well as the transmitted signal. To assess the effect of coarse quantization at the receiver, this paper presents a system level analytic framework based on a simple additive quantization noise model (AQNM). The analysis verified through extensive simulations reveals that at moderate resolutions (3–4 bits per ADC), there is negligible loss in downlink cellular capacity from quantization. In essence, the low resolution ADCs limit the high SNR, where cellular systems typically do not operate. For the transmitter, it is shown that DACs with 4 or more bits of resolution can support high order modulations, and do not violate the adjacent carrier leakage limit set by 3rd Generation Partnership Project (3GPP) New Radio (NR) standards for cellular operations. In fact, our findings suggest that low resolution digital BF architectures can be a power-efficient alternative to analog or hybrid BF for both transmitters and receivers at millimeter-wave. [ABSTRACT FROM AUTHOR]

This article reports signal processing and circuit techniques for direct RF signal modulation. A pulse-encoded transition (PET) technique is introduced to reduce undesired harmonic distortion (HD) and adjacent channel leakage ratio (ACLR) generated by the direct RF modulation. To enable PET RF switching, two variations of a high-power, stacked-FET switch modulator, an 8- and 12-device stack, are designed in 45-nm silicon on insulator (SOI) CMOS. The switch design uses a tapering design to significantly improve power handling with minimal impact to switching speed. The modulators have $P_{1\,{\mathrm{ dB}}} $ values between 34 and 39 dBm while demonstrating a modulation bandwidth of nearly 500 MHz with a 1-GHz carrier. The input referred third order intercept point (IIP3) is between 46 and 61 dBm. Additionally, ACLR measurements of up to −50 dBc are demonstrated using the proposed PET technique at 30-dBm output power. To the best of our knowledge, this is record power handling and ACLR for a CMOS switch. [ABSTRACT FROM AUTHOR]

The dynamic range of a radio-over-fiber (RoF) link is fundamentally limited by the linearity of electro-optic modulators. Silicon photonic (SiP) processes offer significant potential for integration, but the plasma dispersion effect impacts the realizable spur-free dynamic range (SFDR). This article analyzes the underlying source of nonlinearity in SiP Mach–Zehnder modulator (MZM) and demonstrates fundamental limitations on intermodulation distortion. A SiGe low-noise distributed driver is co-designed for the SiP MZM to linearize and extend the bandwidth over which the SFDR remains high. The RoF transmitter achieves 1–20 GHz bandwidth and an SFDR of 109 dB $\cdot $ Hz2/3 at 11 GHz. To the best of our knowledge, this is the highest SFDR demonstrated for a SiP technology without incorporating predistortion. [ABSTRACT FROM AUTHOR]

Silicon photonics offer a low-cost platform for large-scale RF system integration. Spur-free dynamic range (SFDR) for analog and RF photonic components is limited by electrical and optical characteristics of the p- and n- junction used to produce plasma dispersion. We propose a silicon ring modulator and demonstrate design conditions that balance the phase change between the DC Kerr and plasma dispersion effects to produce a broadband, linear electro-optical conversion. A linear phase shifter is tested within a ring modulator and an SFDR of 98 dB $\cdot$ Hz $^{2/3}$ is measured. With predistortion, the SFDR increases to 108 dB $\cdot$ Hz $^{2/3}$. In addition, the ring supports discrete multitone modulation with 16-QAM subcarriers at a 47 Gbps data rate over a 16 GHz bandwidth. [ABSTRACT FROM AUTHOR]

This paper demonstrates generalized code-selective filters for code-pass and code-reject signal processing at RF. A code-reject scheme using a quarter-wave ($\lambda /4$) impedance transformation is also demonstrated to overcome tradeoffs of insertion loss (IL) and linearity compared to series band-reject $N$ -path filters. A 45-nm CMOS SOI implementation consumes a power of 9.32 mW from 1 to 1.8-V supplies at the frequency of 0.35–1.1 GHz and the chip area is 1.73 mm2. The measured transmit rejection is up to 22.6 dB with 4-dB IL. The in-band third-order-intercept point (IIP3) is up to 22.6 dBm and noise figure (NF) of 4–6 dB depending on the applied codes. [ABSTRACT FROM AUTHOR]

CMOS RF switches support watt-level RF output power while enabling signal processing with high speed. Typically, RF FET switches offer a tradeoff between a power handling and modulation bandwidth. This paper investigates the cause of compression in a FET switch, and the analysis suggests the optimization of the gate driving impedance for a stacked-FET switch. A design methodology is presented to realize watt-level power handling with high fractional bandwidth (FBW). The measurements demonstrate a BPSK modulator that can handle up to 10 W with wide FBW. The high-power, low-insertion loss, and high-modulation bandwidth demonstrate record performance. [ABSTRACT FROM AUTHOR]

An image-selection, two-element transceiver is presented that operates over a large fractional bandwidth (FBW) covering both 71–76 and 81–86 GHz while requiring only 3 GHz of local oscillator (LO) tuning range at the RF mixer. A bidirectional sliding-intermediate frequency (IF) Weaver architecture allows operation in either transmit (TX) or receive (RX) modes. The sliding IF and narrow LO tuning range allow wideband image rejection using only a single-stage polyphase filter. The circuit is implemented in a 90-nm SiGe BiCMOS process and the RF and LO circuitry consume at most 150 and 250 mW, respectively. Measurements show less than ±0.75-dB gain variation over 10 GHz in the TX mode and less than ±1-dB variation over 10-GHz bandwidth in the RX mode. With 16- and 64-quadrature-amplitude modulation (QAM), the error vector magnitude is below −22 and −28.5 dB at the data rates of 12 and 9 Gb/s, respectively. [ABSTRACT FROM AUTHOR]

A 70-GHz two-element bidirectional frontend is demonstrated with linear coupled oscillators in a 90-nm silicon–germanium BiCMOS process. The transmitter has a measured peak output power of 7.2 dBm and a peak conversion gain of 14.5 dB while consuming 47 mA from a 1.8-V supply. The receiver has a peak conversion gain of 9.9 dB and a minimum noise figure of 8.6 dB with a nominal current consumption of 18 mA from a 1.5-V supply. The frontend is integrated with a two-element linear coupled oscillator array and achieves a maximum phase scanning of ±80°. [ABSTRACT FROM PUBLISHER]

This paper presents the first phased array transceiver operating from 71 to 86 GHz using injection-locked oscillators (ILOs) for phase shifting. A folded-cascode ILO is proposed to extend the locking range of an array of oscillators. Frequency multiplication covers a 10-GHz tuning range with 23-dB power gain. Each ILO path covers more than ±300° and exhibits low amplitude variation with respect to phase shift range (<1 dB) and excellent isolation and amplitude error (<0.5 dB) between array elements. A wideband, bidirectional RF front end delivers 10-dBm maximum output power with more than 20-dB conversion gain over the 3-dB bandwidth in the transmit (TX) mode and a minimum 9.5-dB noise figure with more than 20-dB conversion gain in the receive (RX) mode. Low phase noise is demonstrated in the ILO approach over the phase tuning range with −112 dBc/Hz at 1-MHz offset and phase noise variation for different phase shift states under 2.5 dB, corresponding to less than 2° phase error. Array patterns demonstrate the wide scan range, and dynamic measurements show that the transmitter supports up to 6-Gb/s data rate with 256 QAM. The chip has $3.4\times2.1$ mm2 area implementing in the 90-nm BiCMOS technology and consuming 386.4 mW in the TX mode and 286 mW in the RX mode per element. [ABSTRACT FROM AUTHOR]

An $E$ -band (71–86-GHz) bidirectional transceiver is presented in this paper. The time-division duplex architecture avoids transmit (TX)/receive (RX) switches through the use of transistor biasing in the signal path to minimize high-frequency loss. The low-noise amplifier (LNA) and power amplifier (PA) are combined into a wideband PA/LNA circuit, which alleviates the parasitic loading of each circuit through a wideband power combiner. The bidirectional transceiver circuit is implemented in 90-nm SiGe BiCMOS process. In TX mode, the bidirectional transceiver transmits a maximum saturated power of 11 dBm at 78 GHz with a 3-dB bandwidth from 71 to 86 GHz. In RX mode, the maximum 30.6-dB conversion gain and the minimum 6.6-dB noise figure are measured at 73 GHz. The whole RF frontend chip consumes 350.2- and 137.7-mW dc power in TX and RX modes, respectively, including all the RF, IF, and local oscillator amplifiers. The overall chip size is 1.5~\text {mm}\times 0.9 mm including pads. [ABSTRACT FROM AUTHOR]

A series code selective filter (CSF) for full-duplex communication is presented. The CSF passes a desired signal in a frequency band only when the signal is tagged with a pseudonoise (PN) code that matches the code at the filter. This approach is shown to reject a transmit signal in the same band as a desired receive signal. The coded transmitter signal is orthogonal through appropriate code selection from a codebook and the PN sequence spreads the signal energy outside the filter bandwidth (BW). The CSF achieves a self-interference rejection of 23.2 dB over a 10-MHz BW using on-chip generated Walsh codes. The CSF operates from 300 to 675 MHz and consumes 28.2 mA from a 1-V supply at 500 MHz. The CSF achieves an IIP3 of 15.7 dBm. The CSF was implemented in a 45-nm CMOS silicon on insulator process and occupies an area of 0.9 mm2. [ABSTRACT FROM AUTHOR]

This paper reports 45-GHz power amplifier (PA) arrays implemented in 45-nm CMOS silicon-on-insulator, coupled to antenna arrays to enable free-space power combining. A single CMOS chip (2.5\,\times\,4.5 \mm^2) containing eight-unit PAs was developed and its output was fed to a 2\,\times\,2 array of differentially fed patch antennas on a printed circuit board. This array provided an equivalent isotropic radiated power (EIRP) of 40 dBm at 45 GHz with 28 dBm of total RF power generated by the chip. A larger array, composed of four CMOS chips and feeding a 2\,\times\,8 array of antennas, was shown to deliver an EIRP of 50 dBm at 45 GHz, while generating a total RF power of 33 dBm together with an antenna array gain of 17 dB. The dc power consumptions for the \2\,\times\,\2 and the 2\,\times\,8 arrays were 4.9 and 18 W, respectively, with estimated peak power-added efficiencies of 13.5% and 10.7%. [ABSTRACT FROM PUBLISHER]

This paper presents an analog circuit scheme to steer phased-array receivers in the direction of an incoming signal. The proposed circuit technique utilizes a coupled-oscillator array along with a coupled-phased-locked loop to auto-align an N-element receive array towards the direction of the incident RF signal. A four-element receiver array is implemented in 45-nm CMOS SOI process and achieves auto-steering range of \pm 35^\circ from broadside. A three-element version of the array demonstrates higher auto-steering angle covering \pm 70^\circ range. The receiver also performs signal demodulation for the incident modulated RF signal, allowing high-data rate communication. A 60-Mbps 64-QAM modulated RF signal is demodulated with error-vector-magnitude (EVM) less than 4% across the steering angle range. The chip area is 3.45 mm^2 including a pad frame with 30-mW/element power consumption. To the best of authors' knowledge, this is the first demonstration of an analog self-steering array in an integrated circuit. [ABSTRACT FROM AUTHOR]

Analytical techniques to determine the linearity and spur-free dynamic range (SFDR) for phased array receivers are presented. The proposed method eliminates the need for circuit-level simulation of intermodulation distortion in an N-element receiver by characterizing the array SFDR from the SFDR for a single receive channel. The analysis separates the relative impact of array factor, circuit architecture and channel linearity to assess the spatial sensitivity of the receiver to jamming signals. The proposed techniques are applied to a comparison of RF phase-shifting and LO phase-shifting receivers. RF phase-shifting architectures are shown to offer more uniform jammer rejection over the beam-scanning range given the same receiver linearity constraints. [ABSTRACT FROM AUTHOR]

This letter demonstrates a low-power, Q-band, direct-conversion I/Q modulator. The modulator consumes 9 mW power from a 1 V supply and delivers - 9.3~dBm RF power at 39 GHz. The modulator exhibits an EVM of 5.3% for 16QAM at 3 Msymbols/s. The circuit is fabricated in 0.12 \mum SiGe BiCMOS process and occupies an area of 1.5 mm^2. [ABSTRACT FROM PUBLISHER]