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A broadband 28 nm complementary metal–oxide–semiconductor (CMOS) power amplifier was implemented using a distributed amplification design. To develop a model library for high-frequency design, various test patterns for active and passive elements were fabricated and compared through measurements. As a result, a symmetrical n-channel field-effect transistor (NFET) was used as the active device, and a co-planar waveguide (CPW) with floating bottom metal layers was chosen as the transmission line for the passive element. These choices demonstrated superior radio frequency (RF) characteristics at high frequencies compared to other device candidates. Furthermore, to address the low breakdown voltage of CMOS, a triple-stacked FET structure was designed as the gain cell of the distributed power amplifier (DPA). The fabricated DPA showed a maximum small-signal gain of 22 dB and a minimum of 10 dB from DC to 56 GHz, with a maximum saturated output power of 20 dBm and a minimum of 13 dBm from 1 to 39 GHz. Notably, these results were achieved on the first attempt by designing solely based on measurement data from the test patterns. [ABSTRACT FROM AUTHOR]

RF power amplifier (RF PA) finds its application in almost all the areas of electronics, mobile communication being identified as a major area. The paper performs a comparative efficiency analysis of RF power amplifiers operating with a fixed bias and an envelope tracking bias. Simulations are performed using Keysight advanced design system (ADS) tool. A class a RF PA operating at a 12 dB gain is fixed for the work. 16 QAM LTE signal operating at 5 MHz input frequency, with a peak to average power ratio (PAPR) of 6.0 dB is used as input signal. An envelope simulation at 2.5 GHz is performed on the RF power amplifier. Simulation result shows an improvement of 12% in power added efficiency (PAE) at 6 dB back-off and 6.422% in mean PAE while using envelope tracking power amplifiers, compared to RF PA with fixed supply. Envelope tracking power amplifiers reduced AM/AM distortions also by a factor of 0.248. The results obtained are much better than that obtained using a conventional RF PA with fixed bias. RF PA being the most power dissipative block in a mobile handset, improving its efficiency contributes directly to a great improvement in the battery lifetime of mobile phones. The major challenges faced by envelope tracking PA (ETPA) designers in achieving this efficiency improvement is also delineated in the paper. [ABSTRACT FROM AUTHOR]

In this paper, behavioral modeling of a driver amplifier is implemented by using S2P and S2D model setup. By using the standard silicon-based driver amplifier for obtaining the measured results of Scattering (S)- parameters and large signal parameters for temperatures 25°C and 85°C. These parameters are imported into the S2P and S2D models to perform the small signal and large signal analysis at 3 GHz frequency for temperatures 25°C and 85°C. Then, the simulated results are compared with the measured results to verify the efficient utilization of behavioral models. The novelty of this work deals with the simulation study of the characteristics of a silicon-based driver amplifier, which are obtained directly from the measurements. This proposed method is essential for performing hetero-integration of transceiver design, which can be further utilized to improve the efficiency of transceiver for high-frequency band. At last, the study of relative error performance analysis between measured and simulated results of different parameters is carried out and calculated value of NMSE (in %) for S11, S12, S21, S22, gain, pout, 1 dB compression point, ACP, 3rd harmonics, 4th harmonics, and 5th harmonics are 0.0083, 0.0055, 0.0086, 0.011, 0.0844, 0.814, 0.926, 0.71, 0.22, 0.012 and 0.070 respectively. [ABSTRACT FROM AUTHOR]

This paper discusses the process of designing and manufacturing a wideband power amplifier operating in the S-band. To amplify a low power and broadband radio frequency signals from 2.1 GHz to 2.5 GHz, the proposed power amplifier uses a diagram of a two-stages amplification with peak offset amplification frequency 2.3 GHz. The power amplifier is designed with a center frequency difference of 2.2 GHz and 2.4 GHz respectively to achieve a bandwidth of 400 MHz. The proposed power amplifier (PA) uses RF transistor SHF-0589 using gallium arsenide heterostructure field-effect transistor (GaAs HFET) technology for high gain and low power consumption. The complete amplifier achieves power gain 21.1 dB inband 2.1-2.5 GHz and achieve maximum power gain of 22.5 dB at the frequency of 2.4 GHz; the output power rise up to 33 dBm; input reflection coefficient (S11) reaches -19.2 dB and output reflection coefficient reaches -17.2 dB. The designed amplifier circuit can be used for wireless sensor networks operating at S-band. [ABSTRACT FROM AUTHOR]

Purpose: The drift in radiofrequency (RF) power amplifiers (RFPAs) is assessed and several contributing factors are investigated. Two approaches for prospective correction of drift are proposed and their effectiveness is evaluated. Methods: RFPA drift assessment encompasses both intra‐pulse and inter‐pulse drift analyses. Scan protocols with varying flip angle (FA), RF length, and pulse repetition time (TR) are used to gauge the influence of these parameters on drift. Directional couplers (DICOs) monitor the forward waveforms of the RFPA outputs. DICOs data is stored for evaluation, allowing calculation of correction factors to adjust RFPAs' transmit voltage. Two correction methods, predictive and run‐time, are employed: predictive correction necessitates a calibration scan, while run‐time correction calculates factors during the ongoing scan. Results: RFPA drift is indeed influenced by the RF duty‐cycle, and in the cases examined with a maximum duty‐cycle of 66%, the potential drift is approximately 41% or 15%, depending on the specific RFPA revision. Notably, in low transmit voltage scenarios, FA has minimal impact on RFPA drift. The application of predictive and run‐time drift correction techniques effectively reduces the average drift from 10.0% to less than 1%, resulting in enhanced MR signal stability. Conclusion: Utilizing DICO recordings and implementing a feedback mechanism enable the prospective correction of RFPA drift. Having a calibration scan, predictive correction can be utilized with fewer complexity; for enhanced performance, a run‐time approach can be employed. [ABSTRACT FROM AUTHOR]

This paper presents an integrated power amplifier (PA) following the orthogonal load-modulated balanced amplifier (OLMBA) topology. The fixed-phase prototype in this paper is implemented with 22 nm complementary metal oxide semiconductor (CMOS) fully depleted silicon-on-insulator (FDSOI) process. The proposed PA operates at 26 GHz frequency range, where it achieves 19.5 dBm output power, 16.6 dB gain, 15.7% power added efficiency, and 18.3 dBm output 1-dB compression point ($P_{\rm 1\,dB}$). The PA is also tested with high dynamic range modulated signals, and it achieves, respectively, 11.4 dBm and 4.9 dBm average output power (P avg) with 100 MHz and 400 MHz 64-QAM third-generation partnership project/new radio frequency range 2 signals, and 14 dBm P avg with 0.6 Gb/s (120 MHz) single carrier 64-QAM signal, measured at 26 GHz and using −28 dBc adjacent channel leakage ratio and −21.9 dB (8%) error vector magnitude as threshold values. The proposed OLMBA is also compared to a stand-alone quadrature-balanced PA. Modulated measurements show that the stand-alone quadrature-balanced PA has better linearity in deep back-off, but the OLMBA has better efficiency. [ABSTRACT FROM AUTHOR]

In this article, a 7–11.5 GHz 2‐W power amplifier (PA) based on cascode transistors is developed using 0.15‐µm GaAs pHEMT. This design facilitates impedance matching in the broadband range by using a cascode structure. A double‐cascode transistors structure is used as a unit cell to combine radio frequency voltage swings to achieve a broad bandwidth (BW). In addition, power synthesis techniques are used to achieve higher power output. Ultimately, based on the above two structures, a four‐way power‐synthesized PA is designed. The fabricated PA shows a peak power of 33.8 dBm at 9 GHz with a power‐added efficiency (PAE) of 43%. The output power is higher than 32 dBm at frequencies from 6 to 11.5 GHz with a PAE of more than 25%. The fractional 3‐dB output power BW is 80%. The chip area is 3.6 × 1.8 mm2, including the input and output test pads. [ABSTRACT FROM AUTHOR]

The practical implementation of massive multi-user multi-input–multi-output (MU-MIMO) downlink communication systems power amplifiers that are energy efficient; otherwise, the power consumption of the base station (BS) will be prohibitive. Constant envelope (CE) precoding is gaining increasing interest for its capability to utilize low-cost, high-efficiency nonlinear radio frequency amplifiers. Our work focuses on the topic of CE precoding in massive MU-MIMO systems and presents an efficient CE precoding algorithm. This algorithm uses an alternating minimization (AltMin) framework to optimize the CE precoded signal and precoding factor, aiming to minimize the difference between the received signal and the transmit symbol. For the optimization of the CE precoded signal, we provide a powerful approach that integrates the majorization-minimization (MM) method and the fast iterative shrinkage-thresholding (FISTA) method. This algorithm combines the characteristics of the massive MU-MIMO channel with the second-order Taylor expansion to construct the surrogate function in the MM method, in which minimizing this surrogate function is the worst-case of the system. Specifically, we expand the suggested CE precoding algorithm to involve the discrete constant envelope (DCE) precoding case. In addition, we thoroughly examine the exact property, convergence, and computational complexity of the proposed algorithm. Simulation results demonstrate that the proposed CE precoding algorithm can achievean uncoded biterror rate (BER) performance gain of roughly 1 dB compared to the existing CE precoding algorithm and has an acceptable computational complexity. This performance advantage also exists when it comes to DCE precoding. [ABSTRACT FROM AUTHOR]

When it comes to the radio frequency (RF) frontend, power amplifier (PA) is one of the most important functional blocks for dependable wireless transmission. In order to provide the necessary output power, PAs boost and amplify the incoming signal, to ensure that the transmitter's signal reaches the receiver at the necessary distance. The PAs have not yet managed to find place within the transceiver circuit due to its bulky nature. Although rigorous efforts have been made to improve the linearity and efficiency of the PAs, it has come at the cost of increase in chip area. This paper focusses on design of an RFPA in an 18nm FinFET advanced node technology that is adaptable to the Sub-6 GHz frequency band of 5G communication standard so as to provide maximum output power at the operating frequency of 3.5GHz. The single stage PA, thus designed and simulated on Cadence Virtuoso provides a gain of 27.71 dB at a supply voltage of 1V. The bandwidth is 208 MHz, power gain is 25dB and the output power is 6.335 dBm. The simple design with a single transistor paves way for a considerable decrease in the chip area, thus making it possible to be placed within the transceiver chip. [ABSTRACT FROM AUTHOR]

Support vector machine (SVR) has been introduced into the modeling of S‐parameters in radio‐frequency (RF) power amplifiers (PA). The modeling accuracy and speed of SVR are primarily affected by the penalty parameter c and the kernel function coefficient γ. Using the traditional grid search technique to determine these two parameters is time‐consuming and labor‐intensive, and ensuring the model's accuracy is not easy. This article proposes an S‐parameters modeling method based on PSO‐GA‐SVR to improve the SVR's modeling accuracy and speed. The model mainly focuses on particle swarm optimization (PSO) and combines selection, crossover, and mutation operations in genetic algorithms (GA). The fitness values are arranged from small to large in each iteration process, and the first 1/3 are selected for crossover and mutation. Then, the resulting new particle swarms are introduced into the original particle swarm population for searching. On the one hand, PSO‐GA extends the population size and reduces the possibility of falling into local optimization. On the other hand, due to population size expansion, the number of iteration rounds is reduced, and the modeling speed is also increased. The experimental results show that compared to SVR, GA‐SVR, and PSO‐SVR, the proposed PSO‐GA‐SVR can improve the modeling accuracy by more than one magnitude or more while also increasing modeling speed by one magnitude or more. Furthermore, compared with the classical machine learning algorithms such as gradient boosting, random forest, and gcForset, the proposed PSO‐GA‐SVR improves the modeling accuracy by one order of magnitude and the modeling speed by two orders of magnitude more than gradient boosting, random forest, and improves the modeling speed by one order of magnitude more than gcForset. [ABSTRACT FROM AUTHOR]

XGBoost is the optimization of gradient boosting with the best overall performance among machine learning algorithms. By introducing a regularization term into the loss function of gradient boosting, XGBoost can effectively limit the complexity of the model, improve the generalization ability, and solve the overfitting problem. In this paper, XGBoost is first introduced into modeling radio‐frequency (RF) power amplifiers (PA) under different temperatures. Furthermore, the modeling effect of XGBoost is mainly dependent on hyperparameters. As traditional grid search is time‐consuming and labor‐intensive, this paper combines particle swarm optimization (PSO) with XGBoost for searching hyperparameters. The experimental results show that XGBoost can effectively suppress the overfitting problem in gradient boosting while modeling RF PAs in different ambient temperatures. In addition, compared to classic machine learning algorithms, including support vector regression (SVR), gradient boosting, and XGBoost, the proposed PSO‐XGBoost can increase the modeling accuracy by one order of magnitude or more while also increasing the modeling speed by more than one magnitude or more. The PSO‐XGBoost model proposed in this paper can be introduced into modeling other microwave/RF devices and circuits to improve modeling accuracy and reduce modeling time. [ABSTRACT FROM AUTHOR]

This article examines the effects of Bayesian optimization (BO) with different covariance functions on the optimization of a radio frequency power amplifier (RFPA). An initial PA is designed based on a Chebyshev low‐pass topology using a 10 W Gallium Nitride (GaN) transistor. The objective function is established in a novel manner. The performance of the initially designed PA was optimized by using various BO algorithms, including two different acquisition functions and five different covariance functions. Both simulation and measurement results indicate that the kernel squared exponential (KSE) and Matérn32 covariance functions provide the best option for optimizing PA by BO. A broadband power amplifier (PA) operating at a frequency range from 2.5 GHz to 3.5 GHz has been developed with an output power (Pout) greater than 40.8 dBm and a power‐added efficiency (PAE) greater than 65%. [ABSTRACT FROM AUTHOR]

This paper presents a highly efficient 5G New-Radio (NR) RF power amplifier module (PAM). The n77 PAM consists of a high-voltage differential-topology 2 μm GaAs HBT power amplifier, a CMOS controller, a silicon-on-insulator (SOI) switch, an integrated passive device (IPD) bandpass filter, a low-noise amplifier (LNA), and a bi-directional coupler. This PAM generates a saturation output power of 32.7 dBm including the loss of the SOI switch and output filter. The designed n77 PAM is tested with a commercial envelope tracker IC (ET-IC). The designed PAM with an ET-IC achieves an ACLR of −37 dBc at a 27 dBm output power with a DFT-s-OFDM QPSK 100 MHz NR signal and saves a dc power consumption of 950 mW compared to the APT mode. For the CP-OFDM 256QAM with the most stringent EVM requirements, it achieves an EVM of 1.22% at 23 dBm and saves 640 mW compared to the APT mode. [ABSTRACT FROM AUTHOR]

In this paper, two improved ultra-wideband (UWB) balanced power amplifiers based on the flip-chip system-in-package technique and electronic design automation (EDA) are proposed. The conventional approach to system-on-chip (SoC) involves integrating all sub-circuit designs into a single manufacturing process. However, in radio frequency circuits, adopting the SoC approach necessitates intricate matching designs, leading to an increase in development costs. In this study, two types of SiGe unit power amplifiers attempted to achieve a flat S21 response using simpler matching for input/output. The cascode architecture was adopted as the main structure for the first type of unit power amplifier (type I). Subsequently, the design of the second type unit power amplifier was built upon the foundation of the first type, with the only difference being the implementation of two parallel cascode structures (type II), and the primary goal is to enhance both gain and output power compared to the first type. In addition, for this second type unit power amplifier, in conjunction with a quadrature hybrid coupler, the optimal impedance matching value was selected to maintain the flatness of gain across the entire UWB range. Furthermore, the poor performance of S11,22 of these two types of unit power amplifiers was improved by using quadrature hybrid couplers using the WIPD process combined with EDA simulation. Therefore, using flip-chip packaging technology can effectively reduce the increased wafer fabrication costs caused by complex matching designs in active circuits. This improved system has the potential to offer a new practical application for UWB power amplifier design. [ABSTRACT FROM AUTHOR]

Summary: By multiplying with the continuous factor (CF), the conventional Class‐ F/F−1, Class‐J power amplifier (PA) can be expanded to their corresponding continuous modes, resulting in a great degree of freedom for broadband design. However, this method can hardly apply to other types of PAs. In view of this problem, the continuous mode is deeply analyzed from the perspective of equation solving for the first time, and a general theory for high‐efficiency broadband continuous PA design is proposed. In this theory, the continuous impedance space does not rely on a mapping relationship achieved by multiplying with the CF, but on a direct solution of the high‐efficiency equations to obtain the broadband design space. This approach is simpler and has the potential to provide greater design space. As a validation, this theory is used for the analysis of Class‐E PAs and a new continuous Class‐E (NC‐E) PA is presented. With knee‐point voltage and finite harmonics taken into account, this type of PA greatly expands the broadband design space of Class‐E PAs and also has the advantage of harmonic matching. The NC‐E PA is designed and manufactured using GaN HEMT CGH40010F, which achieves 40.6–41.6 dBm output power and 66.2%–74.2% drain efficiency (DE) in the frequency band of 2.5–3.8 GHz. [ABSTRACT FROM AUTHOR]

In this paper, the impact of the bias networks on a radio frequency (RF) power amplifier (PA) is analyzed and discussed comprehensively. Both the different sizes and positions of the bias microstrip line circuit have been studied for a broadband class AB PA. Both simulations and measurements show that the performance of the PA can be greatly improved with the adjustment of the bias circuit by effecting the harmonic impedance of the whole matching circuit. Compared with the existing works, the fabricated PA based on the proposed technique provides the best performance, thereby demonstrating the effectiveness of the developed bias circuit optimization method. [ABSTRACT FROM AUTHOR]

Reliability of communications is of vital importance in military applications. Constellations are connecting coded words at different ends of the communication channel that indicate the correctness of the transmitted message. In this paper, we compare the influence of the selected nonlinearity in the transmit amplifier on the constellation diagrams in radio frequency (RF) geostationary satellite downlink and bit-error-rate (BER). Two cases were analyzed: negligible and severe noise in the communication channel. Considering the cubic, hyperbolic tangent, Saleh, Ghorbani, and Raap models, it is shown that the Raap and Saleh models can be used for the lowest BERs when the noise is negligible. In case of severe noise, it is best to use the Raap model from the set of nonlinearities considered. The ANOVA-test showed that there is a dependence between the Raap and Saleh models in the presence of negligible noise, but not in the presence of severe noise. [ABSTRACT FROM AUTHOR]

The proliferation of radar technology has given rise to a growing demand for advanced, high-performance transmitter front-ends operating in the 24 GHz frequency band. This paper presents a design analysis of a radio frequency (RF) transmitter (TX) front-end operated at a 24 GHz frequency and designed using 65 nm complementary metal-oxide-semiconductor (CMOS) technology for radar applications. The proposed TX front-end design includes the integration of an up-conversion mixer and power amplifier (PA). The up-conversion mixer is a Gilbert cell-based design that translates the 2.4 GHz intermediate frequency (IF) signal and 21.6 GHz local oscillator (LO) signal to the 24 GHz RF output signal. The mixer is designed with a novel technique that includes a duplex transconductance path (DTP) for enhancing the mixer's linearity. The DTP of the mixer includes a primary transconductance path (PTP) and a secondary transconductance path (STP). The PTP incorporates a common source (CS) amplifier, while the STP incorporates an improved cross-quad transconductor (ICQT). The integrated PA in the TX front-end is a class AB tunable two-stage PA that can be tuned with the help of varactors as a synchronous mode to increase the PA bandwidth or stagger mode to obtain a high gain. The PA is tuned to 24 GHz as a synchronous mode PA for the TX front-end operation. The proposed TX front-end showed an excellent output power of 11.7 dBm and dissipated 7.5 mW from a 1.2 V supply. In addition, the TX front-end achieved a power-added efficiency (PAE) of 47% and 1 dB compression point (OP1dB) of 10.5 dBm. In this case, the output power is 10.5 dBm higher than the linear portion of the response. The methodologies presented herein have the potential to advance the state of the art in 24 GHz radar technology, fostering innovations in fields such as autonomous vehicles, industrial automation, and remote sensing. [ABSTRACT FROM AUTHOR]

In this work, a new adaptive digital predistorter (DPD) is proposed to linearize radio frequency power amplifiers (PA). The DPD structure is composed of two sub-models. A Feedback–Wiener sub-model, describing the main inverse nonlinearities of the PA, combined with a second sub-model based on a memory polynomial (MP) model. The interest of this structure is that only the MP model is identified in real time to compensate deviations from the initial behavior and thus further improve the linearization. The identification architecture combines offline measurement and online parameter estimation with small number of coefficients in the MP sub-model to track the changes in the PA characteristics. The proposed structure is used to linearize a class AB 75 W PA, designed by Telerad society for aeronautical communications in Ultra High Frequency (UHF) / Very High Frequency (VHF) bands. The obtained results, in terms of identification of optimal DPD and the performances of the digital processing, show a good trade-off between linearization performances and computational complexity. [ABSTRACT FROM AUTHOR]

This research presents a comparative analysis of design parameters in modern power amplifier (PA) architecture trends in various CMOS nano-meter technologies. The design parameters include the signal gain, linearity, output power, and output power back-off. The resultant parameters are compared using a table, and various parameters of various designs are visually shown for comparison. These comparative findings will provide any designer with practical information to choose the best CMOS PA design for a specific application. The most important RF CMOS PA integrated implementations are addressed in the conclusion section. [ABSTRACT FROM AUTHOR]

Summary: Continuous mode provides better bandwidth performance and constant efficiency by offering greater design flexibility in fundamental and harmonics. However, this mode is mainly applicable to limited classes of power amplifiers (PAs) (such as Class‐F, Class‐J, and their derived types). In view of this problem, this paper proposes a general design theory for high‐efficiency broadband continuous PAs, which can easily extend any waveform of PAs to obtain the continuous impedance space. In theoretical analysis, first, the high‐efficiency equations are analyzed from the perspective of frequency domain. Furthermore, combining time domain constraints, a general continuous mode analysis and solution theory is presented. The theory is applied to the bandwidth expansion of Class‐EF PAs, resulting in a new continuous Class‐EF (C‐EF) mode that maintains constant efficiency while offering greater broadband design freedom. The proposed theory is verified by fabricating a C‐EF PA using GaN HEMT CGH40010F, which demonstrated output power (Pout) ranging from 39.5 to 41.2 dBm and drain efficiency (DE) of 69.5% to 79.2% in the frequency range of 2.5–3.6 GHz. [ABSTRACT FROM AUTHOR]

With the development and popularization of the Beidou-3 navigation satellite system (BDS-3), to ensure its unique short message function, it is necessary to integrate a radio frequency (RF) transmitting circuit with high performance in the BDS-3 terminal. As the key device in an RF transmitting circuit, the RF power amplifier (PA) largely determines the comprehensive performance of the circuit with its transmission power, efficiency, linearity, and integration. Therefore, in this paper, an L-band highly integrated PA chip compatible with 3 W and 5 W output power is designed in InGaP/GaAs heterojunction bipolar transistor (HBT) technology combined with temperature-insensitive adaptive bias technology, class-F harmonic suppression technology, analog pre-distortion technology, temperature-insensitive adaptive power detection technology, and land grid array (LGA) packaging technology. Additionally, three auxiliary platforms are proposed, dedicated to the simulation and optimization of the same type of PA designs. The simulation results show that at the supply voltage of 5 V and 3.5 V, the linear gain of the PA chip reaches 39.4 dB and 38.7 dB, respectively; the output power at 1 dB compression point (P1dB) reaches 37.5 dBm and 35.1 dBm, respectively; the saturated output power (Psat) reaches 38.2 dBm and 36.2 dBm, respectively; the power added efficiency (PAE) reaches 51.7% and 48.2%, respectively; and the higher harmonic suppression ratios are less than −62 dBc and −65 dBc, respectively. The size of the PA chip is only 6 × 4 × 1 mm3. The results also show that the PA chip has high gain, high efficiency, and high linearity under both output power conditions, which has obvious advantages over similar PA chip designs and can meet the short message function of the BDS-3 terminal in various application scenarios. [ABSTRACT FROM AUTHOR]

Summary: Conventional solid‐state power amplifier (SSPA) design approach isolates radio frequency (RF) design from communication theory. In this paper, a unified SSPA design approach is proposed, which optimizes SSPA parameters (bias voltage and input RF signal power) to minimize total DC power consumption while satisfying received SNR constraint specified by the link budget. The effect of SSPA nonlinearity is quantified by the error vector magnitude measured at its output and the corresponding received SNR degradation is analyzed. Using the quantitative metrics for received SNR, it is possible to evaluate highly nonlinear SSPA classes such as Class‐B or deep‐Class AB, which are normally not considered in conventional SSPA design approach to be used in satellite communication applications. [ABSTRACT FROM AUTHOR]

Purpose: The purpose of this study is to show that due to the emergence of the Internet of Things (IoT) industry in recent years, the demand for the higher integration of wireless communication systems with a higher data rate of transmission capacity and lower power consumption has increased tremendously. The radio frequency power amplifier (PA) design is getting more challenging and crucial. A PA for a 2.45 GHz IoT application using 0.18 µm complementary metal oxide semiconductor (CMOS) technology is presented in this paper. Design/methodology/approach: The design consists of two stages, the driver and output stage, where both use a single-stage common source transistor configuration. In view of performance, the PA can deliver more than 20 dB gain from 2.4 GHz to 2.5 GHz. Findings: The maximum output power achieved by PA is 13.28 dBm. As the PA design is targeted for Bluetooth low energy (BLE) transmitter use, a minimum of 10 dBm output power should be achieved by PA to transmit the signal in BLE standard. The PA exhibits a constant output third-order interception point of 18 dBm before PA becomes saturated after 10 dBm output power. The PA shows a peak power added efficiency of 17.82% at the 13.24 dBm output power. Originality/value: The PA design exhibits good linearity up to 10 dBm out the PA design exhibits good linearity up to 10 dBm output power without sacrificing efficiency. At the operating frequency of 2.45 GHz, the PA exhibits a stability k-factor, the value of more than 1; thus, the PA design is considered unconditional stable. Besides, the PA shows the s-parameters performance of –7.91 dB for S11, –11.07 dB for S22 and 21.5 dB for S21. [ABSTRACT FROM AUTHOR]

The individual identification of communication emitters is a process of identifying different emitters based on the radio frequency fingerprint features extracted from the received signals. Due to the inherent non-linearity of the emitter power amplifier, the fingerprints provide distinguishing features for emitter identification. In this study, approximate entropy is introduced into variational mode decomposition, whose features performed in each mode which is decomposed from the reconstructed signal are extracted while the local minimum removal method is used to filter out the noise mode to improve SNR. We proposed a semi-supervised dimensionality reduction method named exponential semi-supervised discriminant analysis in order to reduce the high-dimensional feature vectors of the signals, and LightGBM is applied to build a classifier for communication emitter identification. The experimental results show that the method performs better than the state-of-the-art individual communication emitter identification technology for the steady signal data set of radio stations with the same plant, batch and model. [ABSTRACT FROM AUTHOR]

Wireless communication systems have undergone significant development in recent years, particularly with the transition from fourth generation (4G) to fifth generation (5G). As the number of wireless devices and mobile data usage increase, there is a growing need for enhancements and upgrades to the current wireless communication systems. CMOS transceivers are increasingly being explored to meet the requirements of the latest wireless communication protocols and applications while achieving the goal of system-on-chip (SoC). The radio frequency power amplifier (RFPA) in a CMOS transmitter plays a crucial role in amplifying RF signals and transmitting them from the antenna. This state-of-the-art review paper presents a concise discussion of the performance metrics that are important for designing a CMOS PA, followed by an overview of the trending research on CMOS PA techniques that focuses on efficiency, linearity, and bandwidth enhancement. [ABSTRACT FROM AUTHOR]

A radio frequency quadrupole (RFQ) has been constructed as a front accelerator for a rare isotope accelerator facility. The RFQ has two power couplers that are operated simultaneously for high power operation to accelerate from proton to uranium. Coaxial transmission lines have been adopted to connect each power coupler to the 80 kW solid state power amplifier(SSPA) which is consisted with combiners, circulators and 5 kW unit amplifiers. In this study, the coupling to the cavity with two power couplers was investigated for the failure of RF power units. Moreover, the operation scenario of the RFQ linac was also presented in considering the availability. [ABSTRACT FROM AUTHOR]

This research encompasses both Process-Voltage-Temperature (PVT) considerations and behavioral modeling of two proposed Power Amplifier (PA) designs for wireless communication systems. Process variations, supply voltage changes, and temperature changes provide difficulties for the design and optimization of power amplifiers for wireless communication systems and may have a substantial influence on their effectiveness. PVT analysis and behavioral modeling have been conducted to address the aforementioned challenges and characterize the behavior and performance of the power amplifiers under real-world operating conditions. It investigates the impact of process variations, supply voltage variations, and temperature variations on the performance of the PAs. The insights gained from this analysis contribute to a deeper understanding of the power amplifiers' performance, efficiency, and suitability for specific wireless communication standards, laying the foundation for future advancements in RF power amplifier design. The first design focuses on a Doherty PA (DPA) tailored for lowpower short-range applications complying with the IEEE Wireless Personal Area Network (WPAN) standard. The second design explores an Envelope Tracking (ET) supply bias control for low-power long-range applications conforming to the IEEE Wireless Local Area Network (WLAN) standard. By examining these factors, the research ensures that the PAs exhibit reliable and optimal performance under real-world operating conditions. The PVT corners show a change in gain of only 0.4 dB for DPA and 0.9 dB for ET PA. Furthermore, behavioral modeling is employed to characterize the power efficiency of the envelope tracking PA, along with the current efficiency and quotient current on the load current scale. These models provide valuable insights into the behavior and performance of the PAs at a higher level of abstraction. The results and findings contribute to a deeper understanding of the PA’s performance, efficiency, and suitability for specific wireless communication standards, laying the foundation for future advancements in RF power amplifier design. [ABSTRACT FROM AUTHOR]

This paper presents an automatic piecewise (Auto-PW) extreme learning machine (ELM) method for S-parameters modeling radio-frequency (RF) power amplifiers (PAs). A strategy based on splitting regions at the changing points of concave-convex characteristics is proposed, where each region adopts a piecewise ELM model. The verification is carried out with S-parameters measured on a 2.2–6.5 GHz complementary metal oxide semiconductor (CMOS) PA. Compared to the long-short term memory (LSTM), support vector regression (SVR), and conventional ELM modeling methods, the proposed method performs excellently. For example, the modeling speed is two orders of magnitude faster than SVR and LSTM, and the modeling accuracy is more than one order of magnitude higher than ELM. [ABSTRACT FROM AUTHOR]

The high-power radio frequency source for ion cyclotron heating and current drive of ITER tokamak consists of two identical 1.5 MW amplifier chains. These two chains will be combined using a wideband hybrid combiner with adequate coupling flatness, phase balance, return loss, and isolation response to generate 2.5 MW radio frequency (RF) power in the frequency range of 36 to 60 MHz. As part of the in-house development program at ITER-India, a wideband hybrid combiner with coupling flatness and return loss/isolation better than 0.4 and −25 dB, respectively, has been simulated. A detailed analysis for matched load performance of the hybrid combiner for the output power level of 3 MW as well as mismatched load performance for load power of 2.5 MW with voltage standing wave ratio 2.0 and 3.0 MW with voltage standing wave ratio 1.5 has been performed. Based on the simulation, a prototype model was in-house fabricated, and the simulated results have been validated experimentally in splitter and combiner mode. To evaluate performance as a combiner, two solid-state power amplifiers were combined through the prototype combiner for input power levels up to 2.5 kW on matched and mismatched load conditions. In the power splitter experiment, the RF power level up to 1.5 MW from a single amplifier chain was split through the prototype combiner to be dumped in the high power loads in the frequency range of 36 to 60 MHz. [ABSTRACT FROM AUTHOR]

In this paper, a parasitic-design-aware simulation-based design tool is proposed for highly linear RF power amplifiers. The main aim of the proposed tool is to speed up the design process of RF power amplifiers. In addition, it provides accurate final designs taking into consideration the effect of parasitic components of both active and passive devices. The proposed tool relies on the knowledge of designing highly linear RF power amplifiers. Both the optimization steps and design methodology are presented in this paper. The proposed tool is verified by designing a highly linear RF power amplifier at three different frequencies (7 GHz, 10 GHz, and 13 GHz) using 65 nm technology node. The results show that an OP1 dB higher than 18 dBm, gain/S21 higher than 7 dB, and OIP3 higher than 24 dBm at 6 dB back-off power can be obtained. [ABSTRACT FROM AUTHOR]

This letter proposes a switchable function power amplifier/rectifier using a GaN transistor. A dc single‐pole double‐throw switch is used to switch between the working mode of the circuit from power amplifier (PA) to rectifier and vice‐versa, which greatly reduces the complexity of the circuit. A feedback network with an impedance close to infinity and the input port of the PA always terminated to 50 Ω are utilized to achieve consistent impedance conditions in both PA mode and rectifier mode. Class‐F−1 operation is employed to design the PA/rectifier module. For validation, a PA/rectifier operating at 2.4 GHz is designed and fabricated using a CGH40010F GaN transistor. Measurements show that the implemented module can realize efficiency of over 70% regardless of operating in PA mode or in rectifier mode. Meanwhile, the application of the GaN transistor greatly increases the power capacity of the RF‐DC rectifier mode, which is promising in bi‐directional wireless high‐power application scenarios such as enhanced drone airborne capability. To the best of the authors knowledge, this is the first realization of a switchable PA/rectifier module based on a GaN transistor. [ABSTRACT FROM AUTHOR]

This work presents a fully integrated 140-GHz transmitter (TX) achieving a data rate of 160 Gb/s with ~1-pJ/b efficiency in the 22-nm Intel FinFET technology. The TX leverages a wideband radio frequency digital to analog converter (RF-DAC) architecture with embedded 4:1 multiplexer, and it is integrated with a sub-sampling quadrature phase-locked loop (PLL), frequency tripler, local oscillator (LO) buffers, wideband two-stage power amplifier (PA), and on-chip SRAM/pseudorandom binary sequence (PRBS) for high-speed data generation. The TX achieves 120/160-Gb/s 16 quadratic-amplitude modulation (QAM) with −19/−17-dB error vector magnitude (EVM) at an output power of +1.5/+0.8 dBm. [ABSTRACT FROM AUTHOR]

A hybrid power modulator is presented for the radio frequency (RF) power amplifiers of 5th generation mobile communication technology (5G) new radio (NR) applications. A hybrid power modulator utilizing a two-level switching converter and a broadband and high-efficiency linear amplifier is presented. A further improvement in the efficiency of the circuit is achieved by using an optimized supply voltage of the two-level switching converters of 4.5 V. In this way, the overall efficiency is improved by more than 5% compared to using a 5 V supply voltage. The linear amplifier consists of four stages. In order to improve bandwidth and circuit stability, a compensation circuit is added to the linear amplifier that eliminates the poles of the main amplifier by introducing additional zeros, indirectly pushing the pole distribution out of the bandwidth. Using this approach, the linear amplifier achieves a 3-dB bandwidth of 180 MHz and an efficiency of 51%. The hybrid power modulator achieves a maximum output power of 2.4 W and an efficiency of 86% when tracking a 100 MHz 5G-NR signal under a 4 Ω load in a 180 nm CMOS package. [ABSTRACT FROM AUTHOR]

The RF power amplifier (PA) is a unit in wireless transmitters that strengthens the signal to combat losses in transmission by converting dc electric power to the added RF output power. Over the past decades, with the rapid development of wireless communications, high-efficiency PA design has become one of the most popular topics in both academic research and industrial development as the PA consumes a high portion of the transmitter energy, and thus its power efficiency directly impacts the system performance. In addition, because the PA is the main source of distortion generated by the transmitter, linearity is another concern in PA design, particularly in wideband systems. [ABSTRACT FROM AUTHOR]

In power electronics, diode rectifiers are often regarded as the counterpart of a power amplifier. That is plausible because a power amplifier converts dc energy into RF, and a rectifier works in the reverse. In fact, wireless power transfer systems employ a power amplifier for transmission and a diode rectifier for reception. Therefore, the design theory of rectifiers is supposed to be analogous to that of power amplifiers. Is it straightforward to adapt the amplifier theory for rectifiers? [ABSTRACT FROM AUTHOR]

Envelope tracking is a dynamic supply modulation technique, which is mainly used to improve the efficiency of radio frequency power amplifier. For 5G NR mobile devices, this paper presents an envelope tracking supply modulator which is composed of a three-level switching converter and linear amplifier (LA) in parallel. The hysteresis control method is adopted in the supply modulator to improve the bandwidth of the switching converter and the loop response speed. At the same time, a rail-to-rail input-output class AB linear amplifier is designed to achieve a wide output swing and a super source follower is proposed to reduce the output impedance of LA. Designed with the 180 nm CMOS technology, the supply modulator operated at 5G NR 100 MHz envelope signal. The output power of the modulator reaches 1.5 W for a 6 Ω load resistor and the output swing is 4.3 V at 5.0 V supply, and the maximum efficiency reaches 85%. [ABSTRACT FROM AUTHOR]

Artificial intelligence (AI) provides opportunities to enable high-efficiency wireless communication to dynamically adapt to the local environments and user demands. In this article, a continual learning digital predistortion (DPD) algorithm is proposed to linearize radio frequency (RF) power amplifier (PA) in 6G AI-empowered wireless communication. It is achieved by employing the ability of knowledge retention and knowledge transfer to merge the new PA operating state into the previous model, which makes the model more intelligent when dealing with multiple states. In addition, an augmented self-sensing model is proposed to accurately capture the common characteristics and key dynamic characteristics among different PA operating states to improve the knowledge transfer ability during the continual learning process. The experiments were carried out on a Doherty PA with dynamic configurations associated with power, bandwidth, and signal type. The experimental results have shown that the proposed technique can continuously learn when faced with unpredicted new PA operating states and so as to linearize all known states. The proposed DPD method performs with very low complexity in the long term, which is very suitable for the emerging AI-empowered dynamic scenario. [ABSTRACT FROM AUTHOR]

In this article, we present a novel decomposed vector rotation (DVR)-based recurrent neural network behavioral model for digital predistortion (DPD) of radio frequency (RF) power amplifiers (PAs) in wideband scenarios. By representing memory terms of DVR with recurrent states and redesigning the piecewise modeling, we propose a novel recurrent DVR scheme. To ensure stable operation and enhanced modeling accuracy, we integrate the recurrent DVR into the gated learning mechanism of the modified Just Another NETwork (JANET). Experimental results confirm that the proposed DVR-JANET model provides much improved linearization performance with significantly reduced model complexity compared with the recent existing models. [ABSTRACT FROM AUTHOR]

In this article, a uniform neural network (NN) digital predistortion (DPD) model of radio frequency (RF) power amplifiers (PAs) is proposed for dynamic applications, which is suitable for RF PAs under various operating conditions without updating the coefficients. With the development of communication systems, it is difficult for the DPD to track the nonlinearity of the PA as the operating condition varies frequently. As one of the most promising achievements in recent years, the NN has shown excellent generalization ability, which is applicable to the DPD for scalable applications. In this situation, a uniform neural network model (UNNM), whose structure is a two-stage network, is proposed for scalable output power, scalable bandwidth, or simultaneous scalable power and bandwidth. The experiments are carried out on two sub-6 GHz broadband GaN Doherty PAs (DPAs). The experimental results show that the proposed model can achieve comparable performance without coefficient update in the scalable output power range of about 5 dB and the bandwidth range of 100 MHz, which outperforms the conventional fixed model with better than 3 dB power range and 40 MHz bandwidth range. [ABSTRACT FROM AUTHOR]

Digital predistortion (DPD) is an effective linearization technique for RF power amplifiers (PAs), but conventional full sampling (FS) DPD systems use ADCs with three to five times signal bandwidth, and high-speed ADCs are expensive and power-hungry. In this article, we develop a novel band-limited DPD for reducing feedback sampling rate and acquisition bandwidth based on a general framework for semisupervised learning called manifold regularization (MR), which utilizes the geometry of unlabeled data to construct regularization terms for mitigating the overfitting problem. Considering the properties of DPD, we design a basis MR term and introduce it into the classical MR to obtain the extended MR (ExMR) method. To validate the proposed ExMR DPD method, experiments were conducted on two different RF PAs operating at 2.4 and 39 GHz, respectively. The test results demonstrate that the proposed ExMR DPD can linearize the RF PA with a 40-MHz acquisition bandwidth at 100-MHz input. The proposed method significantly reduces the cost and power consumption of the DPD system in comparison with the conventional FS DPD method, which provides a promising solution for broadband communication systems. [ABSTRACT FROM AUTHOR]

To meet the existing requirements of multiband communication and improve the efficiency and performance of communication RF modules, a concurrent tri-band high-efficiency power amplifier operating in three frequency bands is proposed. The input and output impedance values of concurrent power amplifier is analyzed, and the input and output-matching circuit and bias circuit are designed. Through the impedance compensation principle, the impedance matching of three frequency bands is realized, and the amplifier can maintain high power and high efficiency at three arbitrary wide interval frequencies. To this end, a simultaneous tri-band power amplifier is designed and tested by using transistor CGH40010F. The experimental results show that the peak power of the designed simultaneous tri-band high-efficiency power amplifier is more than 10 W, the power-added efficiency reaches 55~69%, and the amplification gain is about 10 dB at three frequency bands of 2.2, 2.6, and 3.5 GHz. The design of concurrent tri-band high-efficiency power amplifier is flexible, the calculation of microstrip line parameters is simple, and it can work in three frequency bands simultaneously. It provides an effective structure scheme for designing concurrent power amplifiers in transmitting systems. [ABSTRACT FROM AUTHOR]

Single modality wireless power transfer has limited depth for mm-sized implants across air/tissue or skull/tissue interfaces because they either suffer from a high loss in tissue (RF, optical) or high reflection at the medium interface [ultrasound (US)]. This article proposes an RF-US relay chip at the media interface avoiding the reflection at the boundary and enables efficient wireless powering to mm-sized deep implants across multiple media. The relay chip rectifies the incoming RF power through an 85.5% efficient RF inductive link (across air) using a multi-output regulating rectifier (MORR) with 81% power conversion efficiency (PCE) at 186 mW load and transmits using adiabatic power amplifiers (PAs) to the implant in order to minimize cascaded power loss. To adapt US focus to implant movement or placement, beamforming was implemented using six channels of US PAs with two-bit phase control (0°, 90°, 180°, and 270°) and three different amplitudes (6–29, 4.5, and 1.8 V) from the MORR. The adiabatic PA contributes a 30%–40% increase in efficiency over class-D and beamforming increases the efficiency by 251% at 2.5 cm over fixed focusing. The proof-of-concept powering system for a retinal implant, from an external PA on a pair of glasses to a hydrophone with 1.2 cm (air) + 2.9 cm (agar eyeball phantom in mineral oil) separation distance, had a power delivered to the load (PDL) of 946 $\mu \text{W}$. The 2.3 mm × 2 mm relay chip was fabricated in a 180 nm high-voltage (HV) BCD process. [ABSTRACT FROM AUTHOR]

A 915 MHz binary frequency-shift keying (BFSK) transmitter (TX) for Internet-of-Things (IoT) applications is presented. The proposed TX adopts a passive frequency tripler, digital duty-cycle/phase calibration, and a low-cost on-chip power amplifier (PA) matching network (MN). The frequency tripler allows an ultralow-power (ULP) implementation of the frequency synthesizer by lowering the maximum operating frequency and relaxing the frequency tuning range requirement. The proposed frequency tripler provides 10.6 dB better 300 MHz spur reduction compared to that of the conventional frequency tripler by adding a series high-pass filter. The two-phase 20% duty-cycle and single-ended 50% duty-cycle calibration circuits drive the frequency tripler and Class-D PA, respectively, suppressing unwanted spurs significantly. The digital duty-cycle/phase calibration circuits, designed based on the quantitative analysis of the stability, offer advantage of technology scaling. The reduced spur relaxes the harmonic filtering requirement at the PA output, leading to an on-chip PA MN with low- ${Q}$. Implemented in 55 nm CMOS, the proposed TX shows the peak output power of 5.2 dBm and efficiency of 30.6% over 902–928 MHz while dissipating 210 $\mu \text{W}$ in the phase-locked loop (PLL) for 0.9 V supply. All spur component levels stay below −41 dBm with the worst harmonic distortion of −48.5 dBc. The proposed TX achieves 100 kbps of data rate for the BFSK modulated signals with the corresponding FSK error of 3.2%. [ABSTRACT FROM AUTHOR]

Wire bonding is widely used in various radio frequency (RF) devices and is one of the common forms of signal interconnection. In this article, a new geometric model with related physical parameters is used to describe various actual types of the bondwire, and the corresponding calculation method for the total length of the bondwire is obtained. Consequently, a new equivalent circuit modeling method of the single‐bondwire can be developed and the accuracy of model has been improved. On this basis, using the concept of partial inductance, the modeling method of double‐bondwire is proposed, which can be applied to asymmetric double‐bondwire modeling. The model of bondwire obtained by this modeling method is applied to the design of PA, and the special electrical properties of the bondwire are used to verify a novel harmonic control method, which second and third harmonics could be controlled. The results show that in the Sub‐6G, the proposed bondwire model has good accuracy, and its performance is close to the measured results. The designed PA combined with harmonic control network has good performance, achieving drain efficiency of 62.6%–70% and output power of 40–41.5 dBm at 3.2–3.8 GHz. It is proved that the proposed bonding line modeling method can be applied to the design of high‐efficient PA. [ABSTRACT FROM AUTHOR]

In this article, a radio-frequency (RF) power-amplifier (PA) system configuration for the on-board energy conversion is proposed for unmanned aerial vehicle base station's (UAV-BS's) battery charging. First, the PA system utilizes the internal RF source for energy conversion so that perpetual battery charging is possible without external power sources. Therefore, a continuous battery charging of the UAV-BS is possible while providing wireless network coverage by hovering over the target location. In addition, the proposed PA system offers a higher RF power control resolution than the existing PA works, which is desirable for precise power control of the UAV-BS. The objective of simultaneous RF power control and battery charging by the PA system is achieved by activating one Wilkinson power divider (WPD) with a specific power splitting ratio in the power divider bank. The simulations show that the dynamic activation of ten distinct unequal split WPDs of the proposed PA system improves the RF power control resolution by $157$ and $396{\,}\%$ compared to the existing PAs. Additionally, the simulations show that the PA's power added efficiency fluctuation is reduced by $54$ and $82{\,}\%$ compared to the existing PAs. In addition, it will be shown that the proposed on-board battery charging increases the hovering time by $7.4{\,}\%$. Furthermore, an energy-efficiency optimization framework for UAV-BS's is proposed considering real-world communication system's hardware imperfections, and the proposed result suggests that UAV-BS's flight time may decrease by $50{\,}\%$ depending upon the type of UAV-BS RF components. [ABSTRACT FROM AUTHOR]

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The necessity of the rapid evolution of wireless communications, with continuously increasing demands for higher data rates and capacity Zheng (Big datadriven optimization for mobile networks toward 5g 30:44–51, 2016), is constantly augmenting the complexity of radio frequency (RF) transceiver architecture. A significant component in the configuration of such complex radio transceivers is the power amplifier(PA). Multiple distributed PAs are now common in proposed RF architectures. PAs exhibit non linear behaviour, causing signal distortion in transmission. Behavioural models offer a concise representation of a PAs characteristic performance which is extremely useful in simulating performance of multiple nonlinear power amplifiers. A considerable drawback with using the Recursive Least Squares (RLS) technique is that the instability of the coefficients during the training of the model. This manuscript provides a computationally efficient technique to detect the onset of instability during adaptive RLS training and subsequently to inform the decision to cease training of dynamic memory polynomial based behavioural models, to avoid the onset of instability. The proposed technique does not require modification of the RLS algorithm, merely an observation of the pre-exsisting autocorrelation function based update. This technique is experimentally validated using four different signal modulation schemes, LTE OFDM, 5G-NR, DVBS2X and WCDMA. [ABSTRACT FROM AUTHOR]