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The non-planar 3D structure of multi-gate FinFETs makes them able to be scaled down to 20 nm and beyond and also have greater performance. But any variation of the fin cross-sectional shape has an impact on the device performance. In this paper, the impact of various fin cross-sectional shape on junctionless accumulation mode bulk FinFETs with thin fins and short channel length has been evaluated. Different important device performance parameters such as ON-current (ION), OFF current (IOFF), ratio of ON/OFF current, Threshold voltage (Vth), Subthreshold swing (SS), drain-induced barrier lowering (DIBL), transconductance (gm), transconductance generation factor (gm/Ids), cut-off frequency (fT), and maximum oscillation frequency (fmax) is evaluated for different fin shapes and analyzed. From the analysis, it is understood that shape of the fin cross-section has substantial impact on performance of the device. Improvement in SCEs was noticed in terms of ~ 25% reduction of DIBL and ~ 10% reduction in SS for the device with reduced fin top width. On the other hand, reduced fin top width degrades the RF performance as maximum frequency of oscillation decrease by ~ 10%. An optimal fin structure for the junctionless bulk FinFET is also obtained to have better SCEs and reasonable Analog/RF applications. [ABSTRACT FROM AUTHOR]

The analog/radio frequency (RF) and linearity performance of a junctionless double gate metal-oxide-semiconductor field-effect transistor (JL DGMOS) is investigated using the numerical TCAD device simulator. JL DGMOSs have shown great promise for high-performance digital applications due to their superior short channel effect performance and ease of fabrication. In analog and RF circuit applications, linearity testing and RF performance is a major issue that is encountered due to non-linear behavior of the devices. Therefore, in this paper, different RF/analog and linearity performance figures of merits such as transconductance, intrinsic gain, the transconductance generation factor, the cut off frequency, the maximum frequency of oscillation, the gain bandwidth product, the variable intercept point of second order, the variable intercept point of third order, inter modulation distortion, the third-order intercept point, and 1-dB compression have been presented. Moreover, the effect of gate-length downscaling on these performance parameters has been carried out. The results indicate that the down scaled JL DGMOS shows great promise to become a competitive contender for analog/mixed signal system on chip applications by demonstrating a significant improvement in its RF performance with gate-length downscaling. [ABSTRACT FROM AUTHOR]

In this paper, the analog/radio frequency (RF) and linearity performance of an InAs-based nanowire (NW) tunnel field-effect transistor (TFET) is studied and compared with InAs-based NW MSFET of identical dimension. InAs-based NW TFETs shows a great promise for high performance digital application because of its superior subthreshold behavior. Different analog/RF and linearity key figure-of-merits like cut-off frequency (ft) and 1-dB compression point are extracted and the effect of gate length down scaling on those parameters has been studied. The results reveal that down scaled InAs-based NW TFET shows a significant improvement in its RF and linearity performance. However, this advantage diminishes in terms of poor analog performance with gate-length downscaling. This clearly indicates the necessity of a trade-off between analog and RF performance. Moreover, an in-depth comparison between InAs-based NW TFET and conventional MOSFET has also been provided in order to demonstrate the superiority of InAs-based NW TFET to become a competitive contender by replacing conventional MOSFET for Analog/Mixed signal System-on-Chip (SOC) applications. Copyright © 2016 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

In this paper, the analog/RF performance of an III–V semiconductor based staggered hetero-tunnel-junction (HETJ) n-type nanowire (NW) tunneling FET (n-TFET) is investigated, for the first time. The device performance figure-of-merits governing the analog/RF performance such as transconductance ( g m ), transconductance-to-drive current ratio ( g m / I DS ), output resistance ( R out ), intrinsic gain and unity-gain cutoff frequency ( f T ) have been studied. The analog/RF performance parameters is compared between HETJ NW TFET and a homojunction (HJ) NW n-type TFET of similar dimensions. In addition to enhanced I ON and subthreshold swing, a significant improvement in the analog/RF performance parameters obtained by the HETJ n-TFET over HJ counterpart for use in analog/mixed signal System-on-Chip (SoC) applications is reported. Moreover, the analog/RF performance parameters of a III–V based staggered HETJ NW TFET is also compared with a heterojunction (HETJ) NW n-type MOSFET having same material as HETJ n-TFET and equal dimension in order to provide a systematic comparison between HETJ-TFET and HETJ-MOSFET for use in analog/mixed-signal applications. The results reveal that HETJ n-TFET provides higher R out and hence, a higher intrinsic gain, an improved g m / I DS ratio, and reasonable f T at lower values of gate-overdrive voltage as compared to the HETJ NW n-MOSFET. [ABSTRACT FROM AUTHOR]

In recent times, InP/InGaAs heterostructure double gate (DG) MOSFET emerges as one of the promising contender for future generation n-MOSFETs design based on its augmented electron mobility. In this work, we have analyzed the influence of gate underlap on the analog and RF performance of InP/InGaAs hetero-junction FET using TCAD device simulation. A comprehensive and quantitative analysis of the key analog and RF figure-of-merits such as drain resistance (RDS), transconductance (gm), cutoff frequency (fT) and maximum frequency of oscillation (fmax) are performed for various underlap length ranging from 2nm to 9nm. Simulation reveals that the analog and RF performance of heterostructure DG MOSFET is severely affected by the amount of underlap length. A trade-off between the analog and RF performance is observed, which can be controlled by a judicious selection of the underlap length. [ABSTRACT FROM AUTHOR]

Abstract: This work uncovers the potential benefit of fully-depleted short-channel triple-material double-gate (TM-DG) SOI MOSFET in the context of RF and analog performance characteristics. A systematic, quantitative investigation of the analog and RF performance figures-of-merits (FOMs) of TM-DG MOSFET are presented. The key idea in this paper is to demonstrate the improved RF, analog and linearity performance exhibited by TM-DG MOSFET over dual-material dual-gate (DM-DG) and conventional single-material double-gate (SM-DG) MOSFET. Using two-dimensional (2-D) device simulations, we have examined various design issues and provided the reasons for the improved performance. The effect of different length ratios of three channel regions related to three different gate materials of TM-DG structure on the RF and analog performance have also been discussed. Simulations reveal an improvement of intrinsic gain by 20.41% and 38.53%, an increase of 14.23% and 26.4% in the case of f T, an increase of 13.9% and 23.85% in the case of f max values for TM-DG (1:2:3) MOSFET compared to DM-DG and SM-DG MOSFET respectively. As a result, we demonstrate that TM-DG MOSFET can be a viable option to enhance the performance of SOI technology for high-frequency analog applications. [Copyright &y& Elsevier]

In this paper, we present a simulation study to report the effect of gate-length downscaling on the analog/RF performance and linearity investigation of InAs-based nanowire (NW) Tunnel FET (TFET). The different RF/analog and linearity figure of merits such as g m , R O , g m* R O , f T , f max, GBW and 1-dB compression point of a NW TFET are extracted and the influence of gate-length downscaling on these parameters is analyzed. The RF/analog performance parameters obtained from InAs TFET is compared with an InAs MOSFET of identical dimension. Results reveal that superior RF and Linearity performance was obtained with gate-length downscaling for both devices under consideration. However, advantages of achieving improved RF performance with gate-length downscaling diminishes in terms of poor analog performance with gate-length downscaling for both the devices. This clearly indicates a trade-off between the analog and RF performance of a down-scaled InAs-based NW TFET and MOSFET. The results reveal that InAs TFET provides better f T , f max and linearity performance in the saturation region than its MOSFET counterpart. It provides a reasonable R O , g m* R O at lower values of gate-overdrive voltage as compared to the InAs MOSFET. Therefore, this paper concludes that InAs NW TFETs have enormous potential to be a promising contender to the conventional bulk MOSFETs for realization of future generation low-power analog/RF applications. [ABSTRACT FROM AUTHOR]