Author: "Ahn, Hong Keun" / Topic: random access memory - Searchworks@Jio Institute Digital Library Search Results

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Start Over Author "Ahn, Hong Keun" Topic random access memory

Author: Choi, Sara, Ahn, Hong Keun, Song, Byungkyu, Kang, Seung H., and Jung, Seong-Ook
Subjects: *PHASE change memory, *RANDOM access memory, *DETECTOR circuits
Abstract: Essential design requirements for a sense amplifier (SA) used in the resistance monitoring write termination (RM-WT) scheme are suggested to reduce the write energy of spin-transfer-torque random access memory (STT-RAM) while achieving a write pass yield comparable to that of a conventional write operation. In addition, a self-referenced single-ended RM-WT (SS-RM-WT) scheme is proposed. To reduce the offset voltage, a single-ended sensing circuit (SE-SC) is used in the SA. A data-aware input voltage-transfer method is also adopted in the SE-SC to maximize the input voltage difference. By adopting a capacitor between the output of the SE-SC and the input of an inverter generating a logical output used for the write termination, the conflict between maintaining and changing the output of the SE-SC is resolved. The simulation results using the industry-compatible 65-nm technology HSPICE model parameters show that the proposed SS-RM-WT scheme achieves a 44% write energy saving on average without increasing the write error rate. Area overhead is only 11.8% for a 256-kb STT-RAM array, whereas that of the previous self-referenced RM-WT schemes is up to 42.5%. [ABSTRACT FROM AUTHOR]
Published: 2021
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Author: Choi, Sara, Ahn, Hong Keun, Song, Byung Kyu, Kim, Jung Pill, Kang, Seung H., and Jung, Seong-Ook
Subjects: COMPUTER memory management, DECODERS & decoding, ERROR correction (Information theory)
Abstract: In this paper, a double-error-correcting and triple-error-detecting (DEC-TED) Bose–Chaudhuri–Hocquenghem (BCH) code decoder with high decoding efficiency and low power for error correction in emerging memories is presented. To increase the decoding efficiency, we propose an adaptive error correction technique for the DEC-TED BCH code that detects the number of errors in a codeword immediately after syndrome generation and applies a different error correction algorithm depending on the error conditions. With the adaptive error correction technique, the average decoding latency and power consumption are significantly reduced owing to the increased decoding efficiency. To further reduce the power consumption, an invalid-transition-inhibition technique is proposed to remove the invalid transitions caused by glitches of syndrome vectors in the error-finding block. Synthesis results with an industry-compatible 65-nm technology library show that the proposed decoders for the (79, 64, 6) BCH code take only 37%–48% average decoding latency and achieve more than 70% power reduction compared to the conventional fully parallel decoder under the 10−4–10−2 raw bit-error rate. [ABSTRACT FROM AUTHOR]
Published: 2019
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