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This article reveals the leakage mechanisms corresponding to the dominant leakage path of individual tail cells in $2\times $ nm technology double data rate (DDR)4 DRAM at operating temperature. For leakage path determination, activation energy (${E}_{a}$) was used as a tool through its extraction by retention time measurement. To get a wide distribution of ${E}_{a}$ , retention testing was performed at the target retention time (10, 15, 20, or 25 s); during this, the number of retentions failed cells were recorded with each temperature. In this experiment, 1.65 e−2% of the selected bank cells found retention failures. From the total retention failed cells, the selected commonly retention failed cells at the target retention times comprise 1.5 e−3% of the selected bank cells. From commonly retention failed cells, the distribution of ${E}_{a}$ is analyzed with the retention time at room temperature. This analysis reveals that subthreshold, junction, and gate-induced drain leakage (GIDL) leakage paths dominate in 3.48%, 93.89%, and 2.61% of the total retention failed cells, respectively, at room temperature. Using another experimental approach, retention testing performed at operating temperature on selected 0.07-ppm retention tail cells concludes that GIDL is the dominant leakage path in this device. Correlation between ${E}_{a}$ and retention time measured at operating temperature (40 °C, 60 °C, or 80 °C) explored the leakage mechanisms corresponding to ${E}_{a}$ of the extracted dominant leakage path (GIDL). These failure leakage mechanisms, dominating on certain values of operating temperature, are divulged as the root cause of failure at that temperature. [ABSTRACT FROM AUTHOR]

Dynamic random access memory (DRAM) bits can be erroneously flipped when the row near the error bits is repeatedly accessed with the activate and precharge commands in a process called row hammering. The trap at an Si–SiO2 interface has been previously reported as the leading cause of such errors. The number of row hammering required for flipping bits initially decreases and then saturates with the increases in the row precharge time ($t_{\mathrm {RP}}$). The DRAM timing parameter is the time interval between an activate command and a precharge command. This study uses the saturation $t_{\mathrm {RP}}$ to estimate the electron emission time of the trap associated with a DRAM bit error. During $t_{\mathrm {RP}}$ time, the traps at the Si–SiO2 interface emit the trapped electrons. There are more chances of emission as $t_{\mathrm {RP}}$ increases, and less row hammering is needed. The emission time of a trapped electron is experimentally measured herein using commercial DDR4 components. The components are irradiated with gamma rays to induce the interface traps. The trap characteristics are then extracted without requiring an additional measurement setup with a device-level preparation. The trap energies with respect to the mid-band at the Si–SiO2 interface are 0.118–0.280 eV. The trap energies are distributed within approximately 5.6 kT energies at room temperature. [ABSTRACT FROM AUTHOR]

In this article, we investigate neutron-induced failures of the Galaxy S7 Edge smartphone (released 2016). Anomalous changes in the neutron-irradiated Galaxy smartphone are described in detail (e.g., device current increments up to 270 mA or overheating in the proximity of the WiFi module). The discussion of system failures includes not only visual observations, but also changes in the current and device temperature of the target smartphone. The system behavior associated with failure modes is also discussed in an effort to relate single-event effects to system malfunctions. Additionally, the test results are compared to similar studies of five products (released 2007–2015). In comparison to the failure rates among those products, the system-level failure-in-time (FIT) did not show a downward trend, although the FIT per megabit (FIT/Mbit) values of static random access memory (SRAM) declined as the technology node shrank. [ABSTRACT FROM AUTHOR]

Static random access memory (SRAM)-based ternary content addressable memory (TCAM) offers TCAM functionality by emulating it with SRAM. However, this emulation suffers from reduced memory efficiency while mapping the TCAM table on SRAM units. This is due to the limited capacity of the physical addresses in the SRAM unit. This brief offers a novel memory architecture called a resource-efficient SRAM-based TCAM (REST), which emulates TCAM functionality using optimal resources. The SRAM unit is divided into multiple virtual blocks to store the address information presented in the TCAM table. This approach virtually increases the overall address space of the SRAM unit, mapping a greater portion of the TCAM table in SRAM and increasing the overall emulated TCAM bits/SRAM at the cost of reduced throughput. A $72 \times 28$ -bit REST consumes only one 36-kbit SRAM and a few distributed RAMs via implementation on a Xilinx Kintex-7 field-programmable gate array. It uses only 3.5% of the memory resources compared with a conventional SRAM-based TCAM (hybrid-partitioned TCAM). [ABSTRACT FROM PUBLISHER]

This paper explores the effectiveness of error detection schemes in increasingly multiple-cell upset-dominant technologies, specifically SRAM. A review of interleaving distance, parity codes, and well-taps is conducted to examine each attribute. Then, the paper proposes a novel error detection scheme with the harmonious use of the multiple-cell upset inhibition effects of well-taps, the detectability of parity codes, and an interleaving distance scheme to create an effective error detection scheme that is both flexible and has a high implementation prospect. A row depth model is created to assess the effectiveness of the proposed scheme. The model shows that advanced technologies with greater multiple-cell upset sizes and ratios will experience error detection failures with schemes such as single error correction-double error detection, whereas the proposed scheme remains effective. Experimental data supports the premise that well-taps inhibit multiple-cell upset, as it is found that 1% cross well-taps. The proposed scheme is recognized to be at least three times better against error detection failures than single error correction-double error detection. [ABSTRACT FROM PUBLISHER]

The physical distance between adjacent memory cells is rapidly decreasing as memory density increases and technology geometry shrinks. As a result of the narrower distance, the capacitance between adjacent cells, which are referred to as the cell coupling capacitor (CCCP), increases and behaves as the source of crosstalk. The crosstalk is further aggravated by increasing operational speeds. When the sizes of the CCCP are marginal, they may not be detected by normal test patterns but can appear when various stresses accumulate. When they are not detected in an early manufacturing stage, they become the source of intermittent failures. Creating a complex test environment is sometimes rejected at the expense of higher parts per million of a device. In this paper, a negative voltage stress is applied to bit lines to test and diagnose the issues from the marginal CCCP. The negative voltage level is closely correlated to the CCCP size, which implies that the proposed method can be used as a vehicle to diagnose the potential issues due to cell coupling capacitors. The simulation results demonstrated that the negative stress voltage can screen the cell coupling capacitors from a few femtofarads to tens of femtofarads in an experimental circuit. The proposed technique has been validated by test chip using 130-nm technology. [ABSTRACT FROM PUBLISHER]

The soft error rates of memories are increased by high-energy particles as technology shrinks. Single-error correction codes (SEC), scrubbing techniques, and interleaving distance (ID) schemes are the most common approaches for protecting memories from soft errors. It is essential to employ analytical models to guide the selection of the interleaving distance; relying on rough estimates may lead to unreasonable design choices. The analytical model proposed in this paper includes the row clustering effects of the accumulated upsets, and was able to estimate the failure probability with a difference of only 0.015% compared to the test data for a 45 nm static random access memory (SRAM) design. [ABSTRACT FROM AUTHOR]