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Processing-in-memory (PIM) architecture has been proposed to accelerate state-of-the-art neuro-inspired algorithms, such as deep neural networks. In this article, we present PIMulator-NN, an event-driven, cross-level simulation framework for PIM-based neural network accelerators. By employing an event-driven simulation mechanism, PIMulator-NN is able to model architecture details and capture design details of the architecture. Moreover, we integrate the main-stream circuit-level simulation framework with PIMulator-NN to accurately simulate the area, latency, and energy consumption of analog computation units. To demonstrate the usage of PIMulator-NN, we implement several PIM designs with PIMulator-NN and perform detailed simulation. The simulation results show that memory access and interconnects make considerable impacts on system-level performance and energy. Note that such results are hard to be captured by conventional performance model-based estimations. We found some anti common-sense results while modeling the architecture details with PIMulator-NN. With several architecture templates, PIMulator-NN provides the users with a platform to build up their PIM architecture quickly. PIMulator-NN is able to capture the impacts of different design choices (e.g., dataflow, interconnect, data parallelism, etc.), and this could enable users to explore their design space efficiently. [ABSTRACT FROM AUTHOR]

Impact of heavy-ion irradiation on the TaOx-based resistive random-access memory (RRAM) is investigated in this work. After Br ion irradiation, the set voltage of TaOx-based RRAM shows slight change, and negative shift of the forming voltage is observed. For the resistance change of TaOx-based RRAM devices induced by irradiation, the resistance of the low resistance state (LRS) illustrates acceptable change, while the resistance of the high resistance state (HRS) is quite sensitive to heavy ion irradation. Some irradiated devices even change from the HRS into the LRS, which results in disappeared memory window and may be attributed to the displacement damage in the dielectric layer. These results indicate that TaOx-based RRAM devices need to be carefully designed for future space applications. [ABSTRACT FROM PUBLISHER]

In this brief, the total ionizing dose (TID) effects of \gamma rays generated from a ^60\Co source on the \TaOx-based resistive switching memory (resistive random-access memory, RRAM) is investigated. The low-resistance state (LRS) of the RRAM is immune to TID effects, whereas the sensitivity of the high-resistance state (HRS) of RRAM to TID effects depends on the dimensions of the device, including the thickness of the oxide film and the area of the device. The HRS of the device with large area and thick oxide layer is vulnerable to TID effects and has a high probability to change into the LRS. Further investigation found that the lower the high resistance, the higher the failure rate of the RRAM device under TID impact, which indicates that the multilevel cell of RRAM should be carefully designed for space system applications considering the radiation effects. The failure of the HRS under TID is explained by defect generation in the oxide film. [ABSTRACT FROM PUBLISHER]

This paper discusses the resistive switching devices based on highly compatible silicon-rich-oxide, including silicon monoxide (SiO) and SiON material, which can be fabricated by low temperature process, and thus fully compatible with the back-end CMOS technology. The demonstrated SiO based RRAM suitable for 3D stackable applications shows repeatable unipolar resistive switching behavior with excellent on/off resistance ratio and good retention performance, but a little bit high switching voltage. The presented silicon-rich silicon-oxynitride RRAM device can effectively reduce the switching voltages (∼1 V) and shows good retention capability under 180°C baking as well as fast speed, giving great potentials for 3D stackable and embedded applications. The switching mechanisms in the studied devices are discussed. The method of switching voltage reduction through nitrogen doping, as a kind of defect engineering, can provide some guidelines for RRAM design. [ABSTRACT FROM AUTHOR]

Abstract: In this paper, high-k LaAlO3 is proposed as tunnel dielectric for p-channel flash memory device application. The program/erase (P/E) injection current characteristic of p-channel flash memory cells with LaAlO3 tunnel dielectric is investigated compared to the cells with SiO2 tunnel dielectric by two-dimensional (2-D) device simulation, which shows that the bit line bias can be lowered from −5V to −3V during both P/E operations of flash memory cells with LaAlO3 tunnel dielectric, meanwhile retains the fast P/E speed and high injection efficiency. Our work also shows that drain disturb, one of the main issues for p-channel flash memory, is alleviated dramatically due to the lower P/E voltage. [Copyright &y& Elsevier]