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A method of using non‐volatile and fast ferroelectric field‐effect transistor (FeFET) devices to realize Boolean logic is proposed. First, the internal states are initialized. Then, the gate and body function as input terminals, which are used to write the states of the device, based on the voltage. Finally, the output signals can be easily read through the drain current. Of the 10 Institute of Electrical and Electronics Engineers (IEEE) standard logic gates, eight can be implemented using the proposed operation method alone and by following the definitions listed herein. Thus, to enable FeFET devices to act as functional logic gates, a simple operating method is proposed, providing substantial contributions to the development of computing in memory. The experimental results provide evidence of the efficacy of this method. [ABSTRACT FROM AUTHOR]

This study investigates the properties of a onetransistor- one-capacitor (1T1C) device that includes a transistor and ferroelectric random access memory (FeRAM) at the nanoscale. The hysteresis characteristics are presented. A simultaneous measurement of writing and reading was used. A difference was observed between the forward and reverse transconductance (gm) −VG curves, and the reason can be explained by the relationship between the operating voltage and coercive voltages. According to the relationship between gm and polarization, the polarization signal can be obtained using gm at the nano-scale. The remnant polarization of the 1T1C device per unit ferroelectric-layer area was confirmed by the polarization value of FeRAM via the Positive Up Negative Down method. Finally, the P–V loops obtained using gm values with different measurement ranges are also reported. [ABSTRACT FROM AUTHOR]

The HfZrOx (HZO) ferroelectric material is a promising material for ferroelectric memory and is compatible with the semiconductor process for ferroelectric random access memory (FeRAM) and negative capacitance field effect transistor. However, defects often exist in the grain boundary to influence the performance or reliability of devices. In addition, uniformity between devices must be considered when they are mass-produced. Therefore, the grain size will become important in determining the performance and reliability. In this study, we use electrical measurements of current–voltage, capacitance–voltage, and polarization–voltage measurements to test high- and low-temperature deposition devices, with a transmission electron microscope (TEM) image to confirm the grain size. Finally, we propose a model to explain the phenomenon and provide a method to obtain better ferroelectric memory. [ABSTRACT FROM AUTHOR]

This paper studies a composite device composed of ferroelectric random access memory (FeRAM) and metal-oxide-semiconductor field effect transistor. The relationship between the hysteresis characteristics and VG is reported, and the on/off ratios under different writing voltages are presented. The gm–VG curve of the forward and reverse sweeping shows that under forward sweep a very clear instability appears while voltage increases. The reasons for this can be explained according to the voltage divider rule, the ID formula, and gm formula of transistors, which show that there is polarization of the ferroelectric material. Accordingly, a method is proposed to determine the critical point of the ferroelectric capacitor polarization in this 1T1C structure, which is advantageous because it identifies the appropriate reading voltage necessary for an effective program state of the 1T1C device. This method was shown in three 1T1C and three FeRAMs devices with different ferroelectric areas. Finally, this method was verified by the P–V loop of FeRAMs. [ABSTRACT FROM AUTHOR]

This work investigates the effect of process temperature on one-transistor-one-capacitor ferroelectric random access memory (1T1C FeRAM) cells fabricated with a HfZrOx ultrathin film applied as the 1T1C capacitor. Traditionally, the capacitor in 1T1C devices is grown on the drain, and such a structure is a type of dynamic memory. Such a structure, however, is prone to the leakage current phenomenon, which causes the amount of charge stored in the capacitor to be insufficient, leading to inaccurate data reading. To solve this problem, an alternative 1T1C structure placing the capacitor on the gate terminal has been proposed. For these alternative 1T1C FeRAM devices, our experimental results indicate that the deposition temperature of the ferroelectric layer has a significant effect on the basic electrical properties. To clarify this phenomenon, we propose a physical model which is based on the effect of the deposition temperature on the HfZrOx grain size. [ABSTRACT FROM AUTHOR]