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Magnetic tunnel junctions (MTJs), as the core storage unit of magneto resistive random-access memory, plays important role in the cutting-edge spintronics. In the MTJ devices, there are multiple internal magnetic/nonmagnetic heterojunction structures. The heterojunction always consists of magnetic metals and magnetic insulators or nonmagnetic metals. The interface of the heterojunction has certain physical effects that can affect the performance of MTJ devices. In the review, combined with the existing research results, the physical mechanism of magnetic/non-magnetic heterojunction interface coupling is discussed. The influence of the interface effect of the heterojunction on the performance of MTJ devices is studied. The optimization method is proposed specifically. This work systematically summarizes the interface effect of magnetic/non-magnetic heterojunction, which could be the critical aspect for the device's yield and reliability. [ABSTRACT FROM AUTHOR]

Inevitable process variations (PVT) brought by both the magnetic tunneling junction (MTJ) and MOSFET based on the complementary metal-oxide semiconductor (CMOS) technology become a major obstacle for the mass production of spin transfer torque magnetic random access memory (STT-MRAM). The detriment of the process variations leads to a serious degradation in the fundamental yield with the shrinkage of the technology nodes. However, the conventional data-cell-variation-tolerant (DCVT) sense scheme cannot get the target read yield due to the limited sense margin (SM). To resolve this problem, a DCVT triple sampling non-destructive self-reference sensing scheme (TSNS) is proposed in the paper, which doubles the SM, with lower power consumption and better SM compared with the conventional DCVT sense scheme. Monte Carlo simulation with industry-compatible 65-nm model parameters results show that the proposed sensing scheme shows over 2.5 times higher SM and less power consumption compared to the previous self-reference circuit. The proposed sensing scheme can get the target read yield with lower power consumption. [ABSTRACT FROM AUTHOR]

Electrically driven magnetization switch has attracted much attention in the new spintronic memory, especially for spin–orbit torque (SOT)-based magnetic random access memory (MRAM). However, the published models are facing limitations with the continuous shrinkage of the feature size down to nanoscale. Also, the thermal effect caused by switching operation is non-negligible. Therefore, an effective model is needed to represent the switching dynamic of the device concerning the influences of the nanoscale and the thermal effect. In the paper, a compact model of three-terminal SOT-driven switching is established. The influence of the voltage-controlled magnetic anisotropy (VCMA) and spin transfer torque (STT) effect induced by bias voltage on the field-free SOT-driven switching is considered by numerically solving the LLG equations. Furthermore, a 3D model of the SOT-MTJ device is established by finite element method to trace the thermoelectric behavior inside the device. The thermoelectric behavior is integrated into the compact model to show the influence of the temperature on the switching behavior, highlighting the importance of the thermal effect for the realistic modelling of SOT-driven switching. Finally, a novel voltage pulse scheme is proposed, which can effectively shorten the switching time and improve the reliability of the device. The established model could provide strategies and guidelines for next-generation memory design and application. [ABSTRACT FROM AUTHOR]

Spin-transfer-torque magnetic random access memory (STT-MRAM) based on magnetic tunnel junction (MTJ) device has attracted significant attention from academics and industries. Nevertheless, the thermal effect under bias operation affects the overall performance and stability of a device. To evaluate the thermal phenomenon in MTJ devices accurately, the non-equilibrium effect between the electron and the phonon near the electrode-barrier interface cannot be ignored. The existence of the interface leads to additional thermal resistance hindering the heat conduction of tunnel junction. Therefore, an effective equivalent model concerning the interface effect is necessary to represent the heat transportation of the device. In this article, a nanoscale thermal transport model of the MTJ device is proposed. The influence of the thermal conductivity of the nano-oxide layer on the temperature distribution is discussed. The interface energy balance transport model is used to clarify the non-equilibrium relationship between the phonon and the electron at the CoFeB/MgO/CoFeB interfaces. A parameterization study is conducted to illustrate the temperature distribution in the nanoscale thermal transport model. Furthermore, the phonon-electron coupling distance ($\delta$) based on the thermal conductivity of the phonon ($\kappa _{p}$) and the electron ($\kappa _{e}$) of the device is implemented to construct the effective equivalent model using finite element modeling (FEM), which could realistically reflect the thermal transport under working conditions. The established equivalent model has a guiding role in exploring the thermal transportation in the nanoscale MTJ device. [ABSTRACT FROM AUTHOR]

A fast writing strategy of spin transfer torque (STT) magnetic random access memory (STT-MRAM) combined with pipeline architecture and early write termination (EWT) technology is proposed in this article. Both the writing speed and the writing power consumption of STT-MRAM are optimized. First, based on the proposed pipeline structure, the writing operation can be conducted within a single clock cycle, much decreasing the writing time. Second, the EWT technology is adopted in the writing operation. In the traditional operation of STT-MRAM, the same data are repeatedly written to the memory cell, which wastes the writing power consumption and the writing operation time. In this article, combined with the EWT technology and the pipeline architecture, the unnecessary writing power is reduced by 92.8%, while the necessary writing power is increased by 19.8%. Taking 32 kb data for the writing operation, the operation speed of the new writing strategy is increased by 67.4% compared with the incumbent writing technology. The proposed strategy has potential application in the embedded STT-MRAM acting as cache memory in the computer system. [ABSTRACT FROM AUTHOR]

Spin transfer magnetoresistive random access memory (STT-MRAM) shows potential applications with the properties of non-volatility, low power consumption and high write/read speed. With the maturity of the STT-MRAM process, it has gradually entered the mass production stage. Reliability will be an important factor limiting the development of this device. Error correction technology is highly required to be developed on this specific memory circuit. In this paper, a combination of low density parity check (LDPC) is used on STT-MRAM, in which the encoding constructs a no 4-girth check matrix. In its fulfillment, the decoded method combines soft decision and hard decision. The simulation results demonstrate that the LDPC shows promising application scenario for STT-MRAM error correction, especially for large-capacity storage arrays. [ABSTRACT FROM AUTHOR]

Spin-Torque-Transfer Magnetic Tunnel Junction (STT-MTJ) device shows wide applications in many important scenarios, including magnetic random access memory (MRAM), logic design, and high-frequency application. Its characterizations at the high frequency are studied intensively recently. In this article, the high-frequency properties of the STT-MTJ device are investigated thoroughly, including a de-embedding approach followed by an extraction procedure for removing the influences from the environment and the package. The de-embedding approach is performed on the STT-MTJ device operated at a high frequency, which can be used to calibrate its electrical characteristics by eliminating the environmental influence. After the calibration, the equivalent circuit for the MTJ device at high frequency can be set up, followed by the extraction procedure of the parasitic parameters of the high-frequency-equivalent-circuit. Combined with the extracted parameters, the equivalent circuit can be used for the simulation work with the MTJ device involved in the high-frequency operation. [ABSTRACT FROM AUTHOR]

• Considered the temperature rise of MTJ in parallel state and anti-parallel state. • Considered the TDDB model in parallel and anti-parallel states. • Considered self-heating effects in the TDDB model. Spin-transfer torque magnetic random access memory (STT-MRAM) is one of the most promising candidates for "universal memory" with the ultra-fast access speed, radiation resistance and theoretically unlimited endurance. However, there are many practical aspects that could degrade the life-time of STT-MRAM. In this paper, degradation on the life-time of the STT-MTJ device is observed experimentally, which is attributed to the so-called "self-heating effect" of the device. Simulation on the device is conducted on the self-heating effect to obtain the internal temperature inside the device. The self-heating effect of the STT-MTJ device is analyzed and its influence on the life-time degradation of the STT-MTJ is included in the time dependent dielectric breakdown model (TDDB, 1/E model). This inclusion should improve the accuracy of the estimation on the life-time. [ABSTRACT FROM AUTHOR]